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SD-A2989-FREQ Datasheet(PDF) 13 Page - Nel Frequency Controls,inc

No. de Pieza. SD-A2989-FREQ
Descripción  Differential Positive ECL (DPECL 3.3V)
Descarga  13 Pages
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Fabricante  NEL [Nel Frequency Controls,inc]
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SD-A2989-FREQ Datasheet(HTML) 13 Page - Nel Frequency Controls,inc

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Besides clock generation and distribution
component considerations, there are other design
subtleties to consider.
Ground plane.
The most important statement that
may not be intuitively obvious to the PCB or sys-
tem designer when moving up to higher frequen-
cies is the absolute requirement for a ground plane.
The ground plane is an integral part of a transmis-
sion line and cannot be omitted. It serves as the
only absolute for all levels, including threshold and
noise margins (excluding the power supply). It is
required for shielding between critical sub-circuits
and to the outside world.
The term ground plane may well refer to an AC
ground, such as that represented by the +5V supply
bus. The +5V plane may be the only solid plane on
the PCB. That is acceptable as long as there is one
which can serve the purpose described.
Circulating currents are generated even if fully dif-
ferential signals are used. The loops swept by these
circulating (output) currents must be minimized
and voltage drops due to such currents must be
taken care of by decoupling capacitors; usually one
0.1µF per IC, placed in close proximity.
Balance and symmetry.
Balance and symmetry
should be maintained for the clocking net and
other time-sensitive data nets. Differential lines
must be of equal length, contain equal loads and
have similar surroundings.
Emissions and crosstalk.
Emissions and crosstalk
can be attributed to two major causes: voltage and
current transients.
Voltage transitions, which are not locally compen-
sated by an equal transition in the reverse direction,
will capacitively couple a noise current of the mag-
nitude C x dV/dt.
Current transients, which are not locally compen-
sated by an equal transition in the reverse direction,
will inductively couple a noise voltage of the mag-
nitude L x dI/dt.
Simultaneous switching of address buses, for
instance, can generate sufficient crosstalk into
ill designed clocking systems to cause runt clock
pulses which are extremely difficult to analyze,
locate and eliminate.
About the Authors
This White Paper was coauthored by NEL Frequency Controls, Inc. and Arizona Microtek Inc. to assist designers in clock
generation and distribution projects for high speed digital system applications.
NEL Frequency Controls, Inc.
, established in 1954, is a crystal oscillator manufacturer specializing in PECL Differential
Clock Oscillators for use in high speed digital design applications. NEL is committed to helping its customers develop effective
clock generation and distribution designs by collaborating with other supply chain partners to deliver complete solutions.
Many of NEL’s products are used in computer, data communication, and instrumentation applications where low jitter and
low emissions are critical requirements. For additional information on frequency management technologies and methods, or
to discuss a specific oscillator application, contact NEL Frequency Controls, Inc. at (414) 763-3591, fax (414) 763-2881,
email, or visit our web site at
Arizona Microtek Inc.
, established in 1985, designs and manufactures ASICs and standard ICs, specializing in mixed-signal
and ultra high speed products. Many of the ASIC products are used in RF wireless or RF over cable applications, while the
standard ICs find applications in data communications applications over optical fiber at data rates of 2.5 Gb/s and faster.
Other product areas address oscillators, clock distributors and buffers, translators and general devices with clock frequencies
of 3 GHz or more and bandwidths of 2 GHz and above-all required in high performance instruments, ATE and serial com-
munications links. For more and updated information, visit AZM’s web site at or call (480) 962-5881
for applications assistance.
Design Subtleties
The latest generation of high speed digital
systems demand better signal integrity. By using
the techniques covered in this design methodology,
designers will greatly reduce system jitter, emissions,
noise generation, and crosstalk. The primary steps
to success are to utilize a PECL differential output
logic clock oscillator that provides fast signal transi-
tions; a PECL differential clock driver; dedicated
PECL-to-CMOS translators for each load point;
and impedance matched and properly terminated
transmission lines.
To support this methodology, it is helpful to
choose component manufacturers who will work
with you, and with one another, in the shared goal
of providing a complete solution. The result will be
faster time-to-market, better product quality, and
improved ability to pass EMI testing requirements.
References used: High-Speed Digital
Design, by Dr. Howard Johnson;
Motorola Application Note AN1406 –
Designing With PECL; Motorola
Application Note AN1405 – ECL
Clock Distribution Techniques.
Copyright ©1999 NEL Frequency
Controls. All rights reserved.

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