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BF1201WR Datasheet(PDF) 7 Page - NXP Semiconductors |
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BF1201WR Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 16 page 2000 Mar 29 7 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR handbook, halfpage 024 6 60 0 20 40 MCD943 VG2-S (V) IG1 ( µA) 4 V 3.5 V 3 V 4.5 V VGG = 5 V Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. VDS = 5 V; Tj =25 °C. RG1 =62kΩ (connected to VGG); see Fig.21. handbook, halfpage 01 2 4 0 −50 −10 3 VAGC (V) gain reduction (dB) −20 −30 −40 MCD944 Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21. VDS = 5 V; VGG = 5 V; RG1 =62kΩ; f = 50 MHz; Tamb =25 °C. handbook, halfpage 0 gain reduction (dB) 10 50 120 110 90 80 100 20 30 40 MCD945 Vunw (dB µV) Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.21. VDS = 5 V; VGG = 5 V; RG1 =62kΩ; f = 50 MHz; funw = 60 MHz; Tamb =25 °C. handbook, halfpage 050 20 0 4 8 12 16 10 20 30 40 gain reduction (dB) ID (mA) MCD946 Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21. VDS = 5 V; VGG = 5 V; RG1 =62kΩ; f = 50 MHz; Tamb =25 °C. |
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