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AD9755AST Datasheet(PDF) 4 Page - Analog Devices |
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AD9755AST Datasheet(HTML) 4 Page - Analog Devices |
4 / 28 page REV. B AD9755 –4– DIGITAL SPECIFICATIONS (T MIN to TMAX, AVDD = DVDD = PLLVDD = CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.) Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 2.1 3 V Logic 0 0 0.9 V Logic 1 Current –10 +10 µA Logic 0 Current –10 +10 µA Input Capacitance 5 pF Input Setup Time (tS), TA = 25 °C 1.0 0.5 ns Input Hold Time (tH), TA = 25 °C 1.0 0.5 ns Latch Pulsewidth (tLPW), TA = 25 °C 1.5 ns Input Setup Time (tS, PLLVDD = 0 V), TA = 25 °C –1.0 –1.5 ns Input Hold Time (tH, PLLVDD = 0 V), TA = 25 °C 2.5 1.7 ns CLK to PLLLOCK Delay (tD, PLLVDD = 0 V), TA = 25 °C 3.5 4.0 ns Latch Pulsewidth (tLPW PLLVDD = 0 V), TA = 25 °C 1.5 ns PLLOCK (VOH) 3.0 V PLLOCK (VOL) 0.3 V CLK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V Min CLK Frequency * 6.25 MHz *Min CLK Frequency only applies when using internal PLL. When PLL is disabled, there is no minimum CLK frequency. Specifications subject to change without notice. |
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