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ADT7486AARMZ-REEL7 Datasheet(PDF) 3 Page - Analog Devices |
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ADT7486AARMZ-REEL7 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 16 page  ADT7484A/ADT7486A Rev. 0 | Page 3 of 16 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY Supply Voltage, VCC 3.0 3.3 3.6 V Undervoltage Lockout Threshold 2.8 V Average Operating Supply Current, IDD 3.8 5 mA Continuous conversions TEMPERATURE-TO-DIGITAL CONVERTER Local Sensor Accuracy +1 ±1.75 °C 40°C ≤ T A ≤ 70°C, V CC = 3.3 V ±5% ±4 °C −40°C ≤ T A ≤ +100°C Remote Sensor Accuracy ±1 °C −40°C ≤ T D ≤ +125°C; T A = 25°C; VCC = 3.3 V +1 ±1.75 °C −40°C ≤ T D ≤ +125°C; −40 ≤T A ≤ 70°C, VCC = 3.3 V ±5% ±4 °C −40°C ≤ T D ≤ +125°C; −40 ≤ T A ≤ +100°C Remote Sensor Source Current 12 μA Low level 80 μA Mid level 204 μA High level Resolution 0.016 °C Series Resistance Cancellation 1.5 kΩ The ADT7484A and ADT7486A cancel 1.5 kΩ in series with the remote thermal diode Conversion Time (Local Temperature)1 12 ms Averaging enabled Conversion Time (Remote Temperature)1 38 ms Averaging enabled Total Monitoring Cycle Time1 50 ms Averaging enabled DIGITAL INPUTS (ADD0, ADD1) Input High Voltage, VIH 2.3 V Input Low Voltage, VIL 0.8 V Input High Current, IIH −1 μA VIN = VCC Input Low Current, IIL 1 μA VIN = 0 Pin Capacitance 5 pF DIGITAL I/O (SST Pin) Input High Voltage, VIH 1.1 V Input Low Voltage, VIL 0.4 V Hysteresis1 150 mV Between input switching levels Output High Voltage, VOH 1.1 1.9 V ISOURCE = 6 mA (maximum) High Impedance State Leakage, ILEAK ±1 μA Device powered on SST bus; VSST = 1.1 V, VCC = 3.3 V High Impedance State Leakage, ILEAK ±10 μA Device unpowered on SST bus; VSST = 1.1 V, VCC = 0 V Signal Noise Immunity, VNOISE 300 mV p-p Noise glitches from 10 MHz to 100 MHz; width up to 50 ns SST TIMING Bitwise Period, tBIT 0.495 500 μs High Level Time for Logic 1, tH12 0.6 × tBIT 0.75 × tBIT 0.8 × tBIT μs tBIT defined in speed negotiation High Level Time for Logic 0, tH02 0.2 × tBIT 0.25 × tBIT 0.4 × tBIT μs Time to Assert SST High for Logic 1, tSU,HIGH 0.2 × tBIT μs Hold Time, tHOLD3 0.5 × tBIT-M μs See SST Specification Rev 1.0 Stop Time, tSTOP 1.25 × tBIT 2 × tBIT 2 × tBIT μs Device responding to a constant low level driven by originator |
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Descripción similar - ADT7486AARMZ-REEL7 |
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