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SMD1108 Datasheet(PDF) 7 Page - Summit Microelectronics, Inc. |
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SMD1108 Datasheet(HTML) 7 Page - Summit Microelectronics, Inc. |
7 / 29 page 7 2052 2.0 10/05/01 SMD1108 Preliminary SUMMIT MICROELECTRONICS, Inc. THE ADC AND THE ANALOG SWITCH 10-bit ADC The 10-bit ADC is a self-clocking SAR implementation. In the manual mode of conversion the sample and hold operation will begin after the SMD1108 has received the request for conversion and the channel address. See Table 1. 8 Analog Channels The eight analog channels can be separated into two function blocks: the bottom four channels (VCC0/CH4 to VCC3/CH7) are primarily supply voltage monitors; the top four channels (CH0 to CH3) are primarily environmental monitors. All eight channels can be switched to the 10-bit ADC and have their inputs converted on-command. CH0 to CH3 may be placed in the Auto-Monitor mode. VCC0/CH4 to VCC3/CH7 provide four inputs to the analog switch that controls the analog inputs to the ADC con- verter. Although these channels cannot be placed in the Auto-Monitor mode, the host can request a direct conver- sion. Because these channels are designed to operate as supply voltage monitors they are each tied into a program- mable comparator. The comparator threshold voltage is programmable and the polarity of the threshold is pro- grammable. This allows very precise monitoring of under- or over-voltage conditions. Paired with each of these DEVICE OPERATION channels is an over-current input (OC0 to OC3) that is offset from its partner comparator by 50mV. TIMER FUNCTIONS WATCHDOG and LONGDOG The SMD1108 has two programmable Watchdog timers each with its own output (WDO# and LDO#) and a com- mon reset input (WLDI). Both are independently program- mable and both can be placed in an idle mode. See Register 8C. RST# This reset output is intended to be used to drive the backend logic. It is an active low open drain output that is driven low whenever VCC0, VCC1, VCC2 or VCC3 is below its programmed threshold and/or MR# is being driven low. It will stay low for the duration of the fault condition or the MR# low input and remain low for the duration of tPURST (the programmed reset pulse width) after removal of the fault condition or MR# returning high. It will also be driven low whenever an over-current condition is detected. See Register 8C. DLYD_RST# This output is activated by the same set of conditions as RST#. However, during a power-up operation it will not be immediately asserted. As soon as power to one of the VCC0/CH4 to VCC3/CH7 inputs is detected a time-out sequence will be started. The time-out period is program- mable and should be equal to or greater than the worst case power-on skew between all the supplies being moni- tored. If all of the supplies have not reached their threshold before the time-out period, DLYD_RST# will be asserted. DLYD_RST# can then be used to disable a voltage sequencer such as the SMH4803A or SMH4804. See Register 8D. OUTPUTS FAULT and HEALTHY Two programmable outputs (active high or active low) that will respond to programmed source activators. See Reg- isters 8F and 90 through 95. IRQs The interrupt outputs are active low open drain outputs that are driven low whenever one of the corresponding monitor inputs senses an excursion beyond its pro- grammed value. See Registers 88, 89, and 98 through 9F. Table 1. Typical ADC Performance 2052 Table01 . C º 5 2 @ o i t a r e s i o N o t l a n g i S. n o m B d 0 7 D H T. n i m B d 0 8 – c i n o m r a h k a e P n o i t a l u d o m r e t n i n o i t r o t s i d r e d r o d n 2. n i m B d 0 8 – r e d r o d r 3. n i m B d 0 8 – 5 2 @ e m i t n o i s r e v n o C º . C. m o n s µ 0 8 y c a r u c c A C D n o i t u l o s e Rs t i b 0 1 g n i s s i m o n h c i h w r o f n o i t u l o s e r m u m i n i M d e e t n a r a u g e r a s e d o c s t i b 0 1 y c a r u c c a e v i t a l e RB S L ½ ± L N DB S L 1 ± r o r r e e l a c s ll u f e v i t i s o PB S L 2 ± r o r r e t e s f f o r a l o p n U V C C V 5 = B S L 2 ± V C C V 6 . 3 o t V 7 . 2 = V C C V 7 . 2 o t V 8 . 1 = |
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