 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
ADSP-21368SKBPZENG Datasheet(PDF) 8 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADSP-21368SKBPZENG Datasheet(HTML) 8 Page - Analog Devices |
|
|
8 / 48 page  Rev. PrA | Page 8 of 48 | November 2004 ADSP-21368 Preliminary Technical Data Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry standard interface com- monly used by audio codecs, ADCs and DACs such as the Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 32 I2S chan- nels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, data- word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be inter- nally or externally generated. The serial ports also contain frame sync error detection logic where the serial ports detect frame syncs that arrive early (for example frame syncs that arrive while the transmission/recep- tion of the previous word is occurring). All the serial ports also share one dedicated error interrupt. S/PDIF Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter The S/PDIF transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the transmitter can be formatted as left justified, I2S or right justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF transmitter are routed through the Signal Routing Unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers. The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz Stereo Asynchronous Sample Rate Converter and provides up to 128dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to con- vert multichannel audio data without phase mismatches. Finally, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Digital Peripheral Interface (DPI) The Digital Peripheral Interface provides connections to two serial peripheral interface ports, two universal asynchronous receiver-transmitters (UARTs), a Two Wire Interface (TWI), 12 Flags, and three general-purpose timers. Serial Peripheral (Compatible) Interface The ADSP-21368 SHARC processor contains two Serial Periph- eral Interface ports (SPIs). The SPI is an industry standard synchronous serial link, enabling the ADSP-21368 SPI compati- ble port to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, sup- porting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI compatible devices, either acting as a master or slave device. The ADSP-21368 SPI compatible peripheral implemen- tation also features programmable baud rate and clock phase and polarities. The ADSP-21368 SPI compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. UART Port The ADSP-21368 processor provides a full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor com- munication capability using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface standard. The UART port also includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation: • PIO (Programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (Direct Memory Access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port's baud rate, serial data format, error code gen- eration and status, and interrupts are programmable: • Supporting bit rates ranging from (fSCLK/ 1,048,576) to (fSCLK/16) bits per second. • Supporting data formats from 7 to12 bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The UART port’s clock rate is calculated as: Where the 16-bit UART_Divisor comes from the DLH register (most significant 8 bits) and DLL register (least significant 8bits). In conjunction with the general-purpose timer functions, auto- baud detection is supported. UART Clock Rate f SCLK 16 UART_Divisor × --------------------------------------------------- = |
Número de pieza similar - ADSP-21368SKBPZENG |
|
Descripción similar - ADSP-21368SKBPZENG |
|
|
Enlace URL |
| Política de Privacidad |
| ALLDATASHEET.ES |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
