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ADSP-BF542 Datasheet(PDF) 2 Page - Analog Devices |
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ADSP-BF542 Datasheet(HTML) 2 Page - Analog Devices |
2 / 64 page Rev. PrG | Page 2 of 82 | December 2007 ADSP-BF542/4/7/8/9 Preliminary Technical Data TABLE OF CONTENTS General Description ................................................. 3 Low-Power Architecture ......................................... 4 System Integration ................................................ 4 ADSP-BF542/4/7/8/9 Processor Peripherals ................ 4 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 5 DMA Controllers ................................................ 10 Real-Time Clock ................................................. 11 Watchdog Timer ................................................ 12 Timers ............................................................. 12 Up/Down Counter and Thumbwheel Interface .......... 12 Serial Ports (SPORTs) .......................................... 12 Serial Peripheral Interface (SPI) Ports ...................... 13 UART Ports (UARTs) .......................................... 13 Controller Area Network (CAN) ............................ 13 TWI Controller Interface ...................................... 14 Ports ................................................................ 14 Pixel Compositor (PIXC) ...................................... 14 Enhanced Parallel Peripheral Interface (EPPI) ........... 14 USB On-The-Go Dual-Role Device Controller ........... 15 ATA/ATAPI–6 Interface ...................................... 15 Keypad Interface ................................................. 15 Secure Digital (SD)/SDIO Controller ....................... 15 Code Security .................................................... 15 Media Transceiver Mac Layer (MXVR) .................... 16 Dynamic Power Management ................................ 16 Voltage Regulation .............................................. 17 Clock Signals ...................................................... 17 Booting Modes ................................................... 19 Instruction Set Description .................................... 22 Development Tools .............................................. 22 Designing an Emulator-Compatible Processor Board (Target) ......................................................... 22 Related Documents .............................................. 22 Pin Descriptions .................................................... 23 Specifications ........................................................ 32 Operating Conditions ........................................... 32 Electrical Characteristics ....................................... 34 ESD Sensitivity ................................................... 34 Absolute Maximum Ratings ................................... 35 Package Information ............................................ 35 Timing Specifications ........................................... 36 Power Dissipation ............................................... 64 Test Conditions .................................................. 64 Environmental Conditions .................................... 65 400-Ball CSP_BGA PACKAGE .................................. 67 360-Ball pBGA PACKAGE ....................................... 73 Outline Dimensions ................................................ 79 Surface Mount Design .......................................... 81 Ordering Guide ..................................................... 82 REVISION HISTORY Revision PrG: Corrections and additions to PrF: • Addition of DDR and Mobile DDR Timing parameters. |
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