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AM29PDL129H53 Datasheet(PDF) 9 Page - SPANSION |
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AM29PDL129H53 Datasheet(HTML) 9 Page - SPANSION |
9 / 49 page November 2, 2005 Am29PDL129H 7 PIN DESCRIPTION A21–A0 = 22-bit address bus for 2 x 64 Mb de- vice. A9 supports 12 V autoselect in- puts. DQ15–DQ0 = 16-bit data inputs/outputs/float CE1#, CE2# = Chip Enable Inputs. CE1# controls the 64 Mb in Banks 1A and 1B. CE2# controls the 64 Mb in Banks 2A and 2B. OE# = Output Enable Input WE# = Write Enable VSS = Device Ground NC = Pin Not Connected Internally RY/BY# = Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an em- bedded algorithm or the device is executing a hardware reset opera- tion. WP#/ACC = Write Protect/Acceleration Input. When WP/ACC#= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP/ACC#= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP/ ACC#= 12V, program and erase op- erations are accelerated. VIO = Input/Output Buffer Power Supply (1.65 V to 1.95 V or 2.7 V to 3.6 V) VCC = Chip Power Supply (2.7 V to 3.6 V) RESET# = Hardware Reset Pin LOGIC SYMBOL 22 16 DQ15–DQ0 A21–A0 CE1# OE# WE# RESET# RY/BY# WP#/ACC VIO (VCCQ) CE2# |
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