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ADS5547IRGZT Datasheet(PDF) 3 Page - Texas Instruments |
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ADS5547IRGZT Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 50 page  www.ti.com ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING CONDITIONS ADS5547 SLWS192 – NOVEMBER 2006 over operating free-air temperature range (unless otherwise noted) VALUE UNIT Supply voltage range, AVDD –0.3 V to 3.9 V Supply voltage range, DRVDD –0.3 V to 3.9 V Voltage between AGND and DRGND -0.3 to 0.3 V Voltage between AVDD to DRVDD -0.3 to 3.3 V Voltage applied to VCM pin (in external reference mode) -0.3 to 1.8 V Voltage applied to analog input pins, INP and INM –0.3 V to minimum (3.6, AVDD + 0.3 V) V Voltage applied to input clock pins, CLKP and CLKM -0.3 V to AVDD + 0.3 V V TA Operating free-air temperature range –40 to 85 °C TJ Operating junction temperature range 125 °C Tstg Storage temperature range –65 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT SUPPLIES Analog supply voltage, AVDD 3 3.3 3.6 V Digital supply voltage, DRVDD 3 3.3 3.6 V ANALOG INPUTS Differential input voltage range 2 VPP Input common-mode voltage 1.5 ±0.1 V Voltage applied on VCM in external reference mode 1.45 1.5 1.55 V CLOCK INPUT Input clock sample rate (1) MSPS DEFAULT SPEED mode 50 210 MSPS LOW SPEED mode 1 60 Input clock amplitude differential (V(CLKP) - V(CLKM)) Sine wave, ac-coupled 0.4 1.5 VPP LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP LVCMOS, single-ended, ac-coupled 3.3 V Input clock duty cycle (See Figure 31) 35% 50% 65% DIGITAL OUTPUTS CL Maximum external load capacitance from each output pin to DRGND (LVDS and CMOS modes) Without internal termination (default after 5 pF reset) With 100 Ω internal termination (2) 10 pF RL Differential load resistance between the LVDS output pairs (LVDS mode) 100 Ω Operating free-air temperature –40 85 °C (1) See the section on Low Sampling Frequency Operation for more information. (2) See the section on LVDS Buffer Internal termination for more information. 3 Submit Documentation Feedback |
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