FM8P51
Rev1.2 Mar 15, 2005
P.8/FM8P51
FEELING
TECHNOLOGY
2.0 FUNCTIONAL DESCRIPTIONS
2.1 Operational Registers
2.1.1 INDF (Indirect Addressing Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
00h (r/w)
INDF
Uses contents of FSR to address data memory (not a physical register)
The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the
register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to the
INDF register indirectly results in a no-operation (although status bits may be affected).
The bits 5-0 of FSR register are used to select up to 64 registers (address: 00h ~ 3Fh).
In FM8P51 series, the data memory is partitioned into four banks. Switching between these banks requires the RP1
and RP0 bits in the FSR register to be configured for the desired bank. The lower locations of each bank are
reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers.
All Special Function Registers and some of General Purpose Registers from other banks are mirrored in bank 0 for
code reduction and quicker access.
Accessed
Bank
RP1:RP0
0
0 0
1
0 1
2
1 0
3
1 1
EXAMPLE 2.1: INDIRECT ADDRESSING
‧
Register file 38 contains the value 10h
‧
Register file 39 contains the value 0Ah
‧
Load the value 38 into the FSR Register
‧
A read of the INDF Register will return the value of 10h
‧
Increment the value of the FSR Register by one (@FSR=39h)
‧
A read of the INDR register now will return the value of 0Ah.
FIGURE 2.1: Direct/Indirect Addressing for FM8P51 Series
Direct Addressing
Indirect Addressing
RP1:RP0
5
from opcode
0
5 from FSR register 0
0 0
0 1
1 0
1 1
location select
00h
location select
addressing INDF register
3Fh
bank select
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