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AD8153 Datasheet(PDF) 12 Page - Analog Devices

No. de Pieza. AD8153
Descripción  Single Buffered Switch 3.2 Gbps
Descarga  18 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD8153 Datasheet(HTML) 12 Page - Analog Devices

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AD8153
Preliminary Technical Data
Rev. PrA | Page 12 of 18
5. Send the register address (8 bits) from which
data is to be read. This transfer should be MSB
first. The register address will be kept in
memory in the AD8153 until the part is reset or
the register address is written over with the
same procedure (steps 1-6).
6. Wait for the AD8153 to acknowledge the
request.
7. Send a repeated start condition (while holding
the SCL line high, pull the SDA line low).
8. Send the AD8153 part address (7 bits) whose
upper 4 bits are the static value b1001 and
whose lower 3 bits are controlled by the input
pins I2C_ADDR[1:0]. This transfer should be
MSB first.
9. Send the read indicator bit (1).
10. Wait for the AD8153 to acknowledge the
request.
11. The AD8153 will then serially transfer the data
(8 bits) held in the register indicated by the
address set in step 5.
12. Acknowledge the data.
13a. Send a stop condition (while holding the SCL
line high, pull the SDA line high) and release
control of the bus.
13b. Send a repeated start condition (while holding
the SCL line high, pull the SDA line low) and
continue with step 2 of the write procedure
(previous section) to perform a write.
13c. Send a repeated start condition (while holding
the SCL line high, pull the SDA line low) and
continue with step 2 of this procedure to
perform a read from a another address.
13d. Send a repeated start condition (while holding
the SCL line high, pull the SDA line low) and
continue with step 8 of this procedure to
perform a read from the same address.
In Figure 5, the AD8153 read process is shown. The SCL signal
is shown along with a general read operation and a specific
example. In the example, data 0x49 is read from address 0x6D
of an AD8153 part with a part address of 0x4B. The part
address is 7 bits wide and is composed of the AD8153 static
upper 4 bits (b1001) and the pin programmable lower 3 bits
(I2C_ADDR[2:0]). In this example, the I2C_ADDR bits are set
to b011. In the figure, the corresponding step number is visible
in the circle under the waveform. The SCL line is driven by the
I2C master and never by the AD8153 slave. As for the SDA line,
the data in the shaded polygons is driven by the AD8153,
whereas the data in the non-shaded polygons is driven by the
I2C master. The end phase case shown is that of 13a.
It is important to note that the SDA line only changes when the
SCL line is low, except for the case of sending a start, stop, or
repeated start condition, as in steps 1, 7, and 13. In Figure 5, A
is the same as ACK in Figure 4. Equally, Sr represents a
repeated start where the SDA line is brought high before SCL is
raised. SDA is then dropped while SCL is still high.
SCL
SDA
General Case
SDA
Example
1
2
2
3
4
5
6
7
8
13a
FIXED PART
ADDR
ADDR
[2:0]
START
R
W
A
REGISTER ADDR
A
DATA
A
STOP
FIXED PART
ADDR
ADDR
[2:0]
Sr
R
W
A
8
9
10
11
12
Figure 5: I2C Read Diagram
I2C TIMING SPECIFICATIONS


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