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AD7980 Datasheet(PDF) 5 Page - Analog Devices

No. de Pieza. AD7980
Descripción  16-bit, 1 MSPS PulSAR ADC in MSOP/QFN
Descarga  22 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD7980 Datasheet(HTML) 5 Page - Analog Devices

 
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Preliminary Technical Data
AD7980
Rev Pr C | Page 5 of 22
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise stated.
Table 4. 1
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data Available
tCONV
350
750
ns
Acquisition Time
tACQ
250
ns
Time Between Conversions
tCYC
1000
ns
CNV Pulse Width ( CS Mode )
tCNVH
10
ns
SCK Period ( CS Mode or Chain mode)
tSCK
ns
VIO Above 4.5 V
10
ns
VIO Above 3 V
10.5
ns
VIO Above 2.7 V
11.5
ns
VIO Above 2.3 V
12.5
ns
VIO Above 1.7 V
14.5
ns
SCK Low Time
tSCKL
3
ns
SCK High Time
tSCKH
3
ns
SCK Falling Edge to Data Remains Valid
tHSDO
3
ns
SCK Falling Edge to Data Valid Delay
tDSDO
VIO Above 4.5 V
7.5
ns
VIO Above 3 V
8
ns
VIO Above 2.7 V
9
ns
VIO Above 2.3 V
10
ns
VIO Above 1.7 V
13
ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
tEN
VIO Above 3 V
10
ns
VIO Above 2.3 V
15
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
15
ns
SDI Valid Setup Time from CNV Rising Edge
tSSDICNV
15
ns
SDI Valid Hold Time from CNV Rising Edge
tHSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSCKCNV
5
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
tSSDISCK
2.5
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
tHSDISCK
3
ns
SDI High to SDO High (Chain Mode with BUSY indicator)
tDSDOSDI
15
ns
1 See Figure 2 and Figure 3 for load conditions.


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