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54F191 Datasheet(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de Pieza. 54F191
Descripción  Up/Down Binary Counter with Preset and Ripple Clock
Descarga  10 Pages
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Fabricante  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
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54F191 Datasheet(HTML) 2 Page - National Semiconductor (TI)

 
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54F74F
Pin Names
Description
UL
Input IIH IIL
HIGHLOW Output IOH IOL
CE
Count Enable Input (Active LOW)
1030
20 mA b18 mA
CP
Clock Pulse Input (Active Rising Edge)
1010
20 mA b06 mA
P0–P3
Parallel Data Inputs
1010
20 mA b06 mA
PL
Asynchronous Parallel Load Input (Active LOW)
1010
20 mA b06 mA
U D
UpDown Count Control Input
1010
20 mA b06 mA
Q0–Q3
Flip-Flop Outputs
50333
b
1 mA20 mA
RC
Ripple Clock Output (Active LOW)
50333
b
1 mA20 mA
TC
Terminal Count Output (Active HIGH)
50333
b
1 mA20 mA
Functional Description
The ’F191 is a synchronous updown 4-bit binary counter It
contains four edge-triggered flip-flops with internal gating
and steering logic to provide individual preset count-up and
count-down operations
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number
When the Parallel Load (PL) input is LOW information pres-
ent on the Parallel Data inputs (P0–P3) is loaded into the
counter and appears on the Q outputs This operation over-
rides the counting functions as indicated in the Mode Se-
lect Table
A HIGH signal on the CE input inhibits counting When CE is
LOW internal state changes are initiated synchronously by
the LOW-to-HIGH transition of the clock input The direction
of counting is determined by the U D input signal as indi-
cated in the Mode Select Table CE and U D can be
changed with the clock in either state provided only that the
recommended setup and hold times are observed
Two types of outputs are provided as overflowunderflow
indicators The Terminal Count (TC) output is normally LOW
and goes HIGH when a circuit reaches zero in the count-
down mode or reaches 15 in the count-up mode The TC
output will then remain HIGH until a state change occurs
whether by counting or presetting or until U D is changed
The TC output should not be used as a clock signal be-
cause it is subject to decoding spikes
The TC signal is also used internally to enable the Ripple
Clock (RC) output The RC output is normally HIGH When
CE is LOW and TC is HIGH the RC output will go LOW
when the clock next goes LOW and will stay LOW until the
clock goes HIGH again This feature simplifies the design of
multistage counters as indicated in
Figures 1 and 2 In Fig-
ure 1 each RC output is used as the clock input for the next
higher stage This configuration is particularly advantageous
when the clock source has a limited drive capability since it
drives only the first stage To prevent counting in all stages
it is only necessary to inhibit the first stage since a HIGH
signal on CE inhibits the RC output pulse as indicated in the
RC Truth Table A disadvantage of this configuration in
some applications is the timing skew between state chang-
es in the first and last stages This represents the cumula-
tive delay of the clock as it ripples through the preceding
stages
A method of causing state changes to occur simultaneously
in all stages is shown in
Figure 2 All clock inputs are driven
in parallel and the RC outputs propagate the carryborrow
signals in ripple fashion In this configuration the LOW state
duration of the clock must be long enough to allow the neg-
ative-going edge of the carryborrow signal to ripple through
to the last stage before the clock goes HIGH There is no
such restriction on the HIGH state duration of the clock
since the RC output of any device goes HIGH shortly after
its CP input goes HIGH
The configuration shown in
Figure 3 avoids ripple delays
and their associated restrictions The CE input for a given
stage is formed by combining the TC signals from all the
preceding stages Note that in order to inhibit counting an
enable signal must be included in each carry gate The sim-
ple inhibit scheme of
Figures 1 and 2 doesn’t apply be-
cause the TC output of a given stage is not affected by its
own CE
Mode Select Table
Inputs
Mode
PL
CE
U D
CP
HL
L
L
Count Up
HL
H
L
Count Down
L
X
X
X
Preset (Asyn)
H
H
X
X
No Change (Hold)
RC Truth Table
Inputs
Output
CE
TC
CP
RC
LH
HX
X
H
XL
X
H
TC is generated internally
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Clock Transition
e
LOW Pulse
2


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