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LP3855-ADJ Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
No. de Pieza. LP3855-ADJ
Descripción  1.5A Fast Response Ultra Low Dropout Linear Regulators
Descarga  16 Pages
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Fabricante  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
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LP3855-ADJ Datasheet(HTML) 6 Page - National Semiconductor (TI)

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Electrical Characteristics
LP3855-ADJ (Continued)
Limits in standard typeface are for T
J = 25˚C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: V
IN =VO(NOM) + 1V, IL = 10 mA, COUT = 10µF, VSD = 2V.
Symbol
Parameter
Conditions
Typ
(Note 4)
LP3855-ADJ (Note 5)
Units
Min
Max
Shutdown Input
V
SDT
Shutdown Threshold
Output = High
V
IN
2
V
Output = Low
0
0.3
T
dOFF
Turn-off delay
I
L = 1.5A
20
µs
T
dON
Turn-on delay
I
L = 1.5A
25
µs
I
SD
SD Input Current
V
SD =VIN
1nA
AC Parameters
PSRR
Ripple Rejection
V
IN =VOUT +1V
C
OUT = 10uF
V
OUT = 3.3V, f = 120Hz
73
dB
V
IN =VOUT + 0.5V
C
OUT = 10uF
V
OUT = 3.3V, f = 120Hz
57
ρ
n(l/f)
Output Noise Density
f = 120Hz
0.8
µV
e
n
Output Noise Voltage
BW = 10Hz – 100kHz
V
OUT = 2.5V
150
µV (rms)
BW = 300Hz – 300kHz
V
OUT = 2.5V
100
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 2: At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO220 package must be derated at
θjA = 50˚C/W
(with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surface-mount package must be derated at
θjA = 60˚C/W (with
0.5in2, 1oz. copper area), junction-to-ambient. See Application Hints.
Note 3: The human body model is a 100pF capacitor discharged through a 1.5k
Ω resistor into each pin.
Note 4: Typical numbers are at 25˚C and represent the most likely parametric norm.
Note 5: Limits are guaranteed by testing, design, or statistical correlation.
Note 6: If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.
Note 7: The output PMOS structure contains a diode between the VIN and VOUT terminals. This diode is normally reverse biased. This diode will get forward biased
if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200mA of DC current and 1Amp
of peak current.
Note 8: Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load
regulation is defined as the change in output voltage from the nominal value due to change in load current.
Note 9: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage
specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential,
since the minimum input voltage is 2.5V.
Note 10: The minimum operating value for VIN is equal to either [VOUT(NOM) +VDROPOUT] or 2.5V, whichever is greater.
Note 11: The SOT 223 package devices have slightly higher dropout due to increased bond wire resistance.
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