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MAX6639 Datasheet(PDF) 3 Page - Maxim Integrated Products

No. de Pieza. MAX6639
Descripción  2-Channel Temperature Monitor with Dual, Automatic, PWM Fan-Speed Controller
Descarga  22 Pages
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Fabricante  MAXIM [Maxim Integrated Products]
Página de inicio  http://www.maxim-ic.com
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MAX6639 Datasheet(HTML) 3 Page - Maxim Integrated Products

 
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2-Channel Temperature Monitor with Dual,
Automatic, PWM Fan-Speed Controller
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +5.5V, TA = 0
°C to +125°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS AND OUTPUTS
ALERT, FANFAIL, THERM, OT, SDA
ISINK = 6mA
0.4
Output Low Voltage (Sink
Current) (OT, ALERT, FANFAIL,
THERM, SDA, PWM1, and PWM2)
VOL
PWM1, PWM2, ISINK = 4mA
0.4
V
Output High Leakage Current
(OT, ALERT, FANFAIL, THERM,
SDA, PWM1, and PWM2)
IOH
1µA
Logic-Low Input Voltage (SDA,
SCL, THERM, TACH1, TACH2)
VIL
0.8
V
VCC = 3.3V
2.1
Logic-High Input Voltage (SDA,
SCL, THERM, TACH1, TACH2)
VIH
VCC = 5.5V
2.6
V
Input Leakage Current (SDA,
SCL, THERM, TACH1, TACH2)
VIN = VCC or GND
1
µA
Input Capacitance
CIN
5pF
SMBus TIMING (Note 2)
Serial Clock Frequency
fSCL
(Note 3)
10
100
kHz
Clock Low Period
tLOW
10% to 10%
4
µs
Clock High Period
tHIGH
90% to 90%
4.7
µs
Bus Free Time Between STOP
and START Conditions
tBUF
4.7
µs
SMBus START Condition Setup
Time
tSU:STA
90% of SMBCLK to 90% of SMBDATA
4.7
µs
START Condition Hold Time
tHD:STO
10% of SDA to 10% of SCL
4
µs
STOP Condition Setup Time
tSU:STO
90% of SCL to 10% of SDA
4
µs
Data Setup Time
tSU:DAT
10% of SDA to 10% of SCL
250
ns
Data Hold Time
tHD:DAT
10% of SCL to 10% of SDA (Note 4)
300
ns
SMBus Fall Time
tF
300
ns
SMBus Rise Time
tR
1000
ns
SMBus Timeout
tTIMEOUT
58
74
90
ms
Note 1: All parameters tested at a single temperature. Specifications are guaranteed by design.
Note 2: Timing specifications guaranteed by design.
Note 3: The serial interface resets when SCL is low for more than tTIMEOUT.
Note 4: A transition must internally provide at least a hold time to bridge the undefined region (300ns max) of SCL's falling edge.


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