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MC68HC08AS32A Datasheet(PDF) 50 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 50 Page - Motorola, Inc

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Memory
Data Sheet
MC68HC08AS32A — Rev. 1
50
Memory
MOTOROLA
2.5.2.4 EEPROM Timebase Divider Register
The 16-bit EEPROM timebase divider register consists of two 8-bit registers:
EEDIVH and EEDIVL. The 11-bit value in this register is used to configure the
timebase divider circuit to obtain the 35
µs timebase for EEPROM control.
These two read/write registers are respectively loaded with the contents of the
EEPROM timebase divider non-volatile registers (EEDIVHNVR and EEDIVLNVR)
after a reset.
EEDIVSECD — EEPROM Divider Security Disable
This bit enables/disables the security feature of the EEDIV registers. When
EEDIV security feature is enabled, the state of the registers EEDIVH and
EEDIVL are locked (including EEDIVSECD bit). The EEDIVHNVR and
EEDIVLNVR non-volatile memory registers are also protected from being
erased/programmed.
1 = EEDIV security feature disabled
0 = EEDIV security feature enabled
EEDIV[10:0] — EEPROM Timebase Prescaler
These prescaler bits store the value of EEDIV which is used as the divisor to
derive a timebase of 35
µs from the selected reference clock source
(CGMXCLK or bus block in the MOR register) for the EEPROM related state
machine and circuits. EEDIV[10:0] bits are readable at any time. They are
writable when EELAT = 0 and EEDIVSECD = 1.
The EEDIV value is calculated by the following formula:
EEDIV = INT [Reference Frequency (Hz) x 35 x 10–6 + 0.5]
Where the result inside the bracket is rounded down to the nearest integer
value. For example, if the reference frequency is 4.9153 MHz, the EEDIV value
is 172.
NOTE:
Programming/erasing the EEPROM with an improper EEDIV value may result in
data lost and reduce endurance of the EEPROM device.
Address: $FE1A
Bit 7
654321
Bit 0
Read:
EEDIVSECD
0000
EEDIV10
EEDIV9
EEDIV8
Write:
Reset:
Contents of EEDIVHNVR ($FE10), bits [6:3] = 0
= Unimplemented
Figure 2-6. EEDIV Divider High Register (EEDIVH)
Address: $FE1B
Bit 7
654321
Bit 0
Read:
EEDIV7
EEDIV6
EEDIV5
EEDIV4
EEDIV3
EEDIV2
EEDIV1
EEDIV0
Write:
Reset:
Contents of EEDIVLNVR ($FE11)
Figure 2-7. EEDIV Divider Low Register (EEDIVL)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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