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MC68HC08AS32A Datasheet(PDF) 56 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 56 Page - Motorola, Inc

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Analog-to-Digital Converter (ADC)
Data Sheet
MC68HC08AS32A — Rev. 1
56
Analog-to-Digital Converter (ADC)
MOTOROLA
configured to derive its internal clock from CGMXCLK and the bus clock is being
derived from the PLL within the CGM [CGMOUT]), this 16-
µs conversion can take
up to 17
µs to complete. This worst-case could occur if the write to the ADSCR
happened directly after the rising edge of the ADC internal clock causing the
conversion to wait until the next rising edge of the ADC internal clock. With a 1-MHz
ADC internal clock, the maximum sample rate is 59 kHz to 62 kHz. Refer to 18.7
ADC Characteristics
3.3.4 Continuous Conversion Mode
In the continuous conversion mode, the ADC continuously converts the selected
channel, filling the ADC data register with new data after each conversion. Data
from the previous conversion will be overwritten whether that data has been read
or not. Conversions will continue until the ADCO bit is cleared. The COCO bit (ADC
status control register, $0038) is set after each conversion and will stay set until the
next read of the ADC data register.
When a conversion is in process and the ADSCR is written, the current conversion
data should be discarded to prevent an incorrect reading.
3.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes. Refer to
18.7 ADC Characteristics for accuracy information.
3.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt
after each ADC conversion. A CPU interrupt is generated if the COCO bit is at
logic 0. The COCO bit is not used as a conversion complete flag when interrupts
are enabled.
3.5 Low-Power Modes
The following subsections describe the low-power modes.
3.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt
request from the ADC can bring the MCU out of wait mode. If the ADC is not
required to bring the MCU out of wait mode, power down the ADC by setting the
ADCH[4:0] bits in the ADC status and control register to logic 1s before executing
the WAIT instruction.
16 to 17 ADC Clock Cycles
Conversion Time =

ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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