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MC68HC08AS32A Datasheet(PDF) 65 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 65 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
Functional Description
MC68HC08AS32A — Rev. 1
Data Sheet
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
65
Use of the BDLC module in message networking fully implements the SAE
Standard J1850 Class B Data Communication Network Interface specification.
NOTE:
It is recommended that the reader be familiar with the SAE J1850 document and
ISO Serial Communication document prior to proceeding with this section of the
MC68HC08AS32A specification.
Figure 4-2. BDLC Block Diagram
CPU INTERFACE
TO J1850 BUS
MUX INTERFACE
PROTOCOL HANDLER
PHYSICAL INTERFACE
TO CPU
BDLC
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$003B
BDLC Analog and Roundtrip
Delay Register (BARD)
See page 84.
Read:
ATE
RXPOL
00
BO3
BO2
BO1
BO0
Write:
R
R
Reset:
1
1
0
0
0
1
1
1
$003C
BDLC Control Register 1
(BCR1)
See page 86.
Read:
IMSG
CLKS
R1
R0
00
IE
WCM
Write:
R
R
Reset:
1
1
1
0
0
0
0
0
$003D
BDLC Control Register 2
(BCR2)
See page 88.
Read:
ALOOP
DLOOP
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
Write:
Reset:
1
1
0
0
0
0
0
0
$003E
BDLC State Vector Register
(BSVR)
See page 93.
Read:
0
0
I3
I2
I1
I0
0
0
Write:
R
R
R
R
RRR
R
Reset:
0
0
0
0
0
0
0
0
$003F
BDLC Data Register
(BDR)
See page 95.
Read:
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
Write:
Reset:
Unaffected by reset
R= Reserved
Figure 4-3. BDLC I/O Register Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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