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MC68HC08AS32A Datasheet(PDF) 68 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 68 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
Data Sheet
MC68HC08AS32A — Rev. 1
68
Byte Data Link Controller-Digital (BDLC-D)
MOTOROLA
elsewhere in the network, including the node’s analog physical interface. In this
mode, the transmit digital output pin (BDTxD) and the receive digital input pin
(BDRxD) of the digital interface are disconnected from the analog physical
interface and tied together to allow the digital portion of the BDLC to transmit and
receive its own messages without driving the J1850 bus.
4.3.1.7 Analog Loopback Mode
Analog loopback is used to determine if a bus fault has been caused by a failure in
the node’s off-chip analog transceiver or elsewhere in the network. The BCLD
analog loopback mode does not modify the digital transmit or receive functions of
the BDLC. It does, however, ensure that once analog loopback mode is exited, the
BDLC will wait for an idle bus condition before participation in network
communication resumes. If the off-chip analog transceiver has a loopback mode,
it usually causes the input to the output drive stage to be looped back into the
receiver, allowing the node to receive messages it has transmitted without driving
the J1850 bus. In this mode, the output to the J1850 bus is typically high
impedance. This allows the communication path through the analog transceiver to
be tested without interfering with network activity. Using the BDLC analog loopback
mode in conjunction with the analog transceiver’s loopback mode ensures that,
once the off-chip analog transceiver has exited loopback mode, the BCLD will not
begin communicating before a known condition exists on the J1850 bus.
4.4 BDLC MUX Interface
The MUX interface is responsible for bit encoding/decoding and digital noise
filtering between the protocol handler and the physical interface.
Figure 4-5. BDLC Block Diagram
CPU INTERFACE
TO J1850 BUS
MUX INTERFACE
PROTOCOL HANDLER
PHYSICAL INTERFACE
TO CPU
BDLC
Freescale Semiconductor, Inc.
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