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MC68HC08AS32A Datasheet(PDF) 69 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 69 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
MC68HC08AS32A — Rev. 1
Data Sheet
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
69
4.4.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low pass filter to remove narrow
noise pulses from the incoming message. An outline of the digital filter is shown in
Figure 4-6.
Figure 4-6. BDLC Rx Digital Filter Block Diagram
4.4.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see fBDLC
parameter in Table 4-3). At each positive edge of the clock signal, the current state
of the receiver physical interface (BDRxD) signal is sampled. The BDRxD signal
state is used to determine whether the counter should increment or decrement at
the next negative edge of the clock signal.
The counter will increment if the input data sample is high but decrement if the input
sample is low. Therefore, the counter will thus progress either up toward 15 if, on
average, the BDRxD signal remains high or progress down toward 0 if, on average,
the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter decides that the
condition of the BDRxD signal is at a stable logic level 1 and the data latch is set,
causing the filtered Rx data signal to become a logic level 1. Furthermore, the
counter is prevented from overflowing and can only be decremented from this
state.
Alternatively, should the counter eventually reach the value 0, the digital filter
decides that the condition of the BDRxD signal is at a stable logic level 0 and the
data latch is reset, causing the filtered Rx data signal to become a logic level 0.
Furthermore, the counter is prevented from underflowing and can only be
incremented from this state.
The data latch will retain its value until the counter next reaches the opposite end
point, signifying a definite transition of the signal.
4-BIT UP/DOWN COUTER
DATA
LATCH
UP/DOWN
OUT
D
Q
FILTERED
RX DATA OUT
MUX INTERFACE
INPUT
SYNC
DQ
RX DATA
FROM
PHYSICAL
INTERFACE
CLOCK
(BDRXD)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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