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MC68HC08AS32A Datasheet(PDF) 75 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 75 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
MC68HC08AS32A — Rev. 1
Data Sheet
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
75
4.4.4 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the J1850 bus have
been defined to allow for variations in oscillator frequencies. In many cases the
maximum time allowed to define a data bit or symbol is equal to the minimum time
allowed to define another data bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol is being
received is equal to a single period of the MUX interface clock (tBDLC), an apparent
separation in these maximum time/minimum time concurrences equal to one cycle
of tBDLC occurs.
This one clock resolution allows the BDLC to differentiate properly between the
different bits and symbols. This is done without reducing the valid window for
receiving bits and symbols from transmitters onto the J1850 bus which have
varying oscillator frequencies.
In Huntsinger’s’ variable pulse width (VPW) modulation bit encoding, the
tolerances for both the passive and active data bits received and the symbols
received are defined with no gaps between definitions. For example, the maximum
length of a passive logic 0 is equal to the minimum length of a passive logic 1, and
the maximum length of an active logic 0 is equal to the minimum length of a valid
SOF symbol.
Invalid Passive Bit
See Figure 4-9(1). If the passive-to-active received transition beginning the
next data bit or symbol occurs between the active-to-passive transition
beginning the current data bit (or symbol) and a, the current bit would be invalid.
Figure 4-9. J1850 VPW Received Passive Symbol Times
a
bc
b
a
(1) INVALID PASSIVE BIT
(2) VALID PASSIVE LOGIC 0
(3) VALID PASSIVE LOGIC 1
64
µs
128
µs
cd
(4) VALID EOD SYMBOL
200
µs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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