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MC68HC08AS32A Datasheet(PDF) 82 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 82 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
Data Sheet
MC68HC08AS32A — Rev. 1
82
Byte Data Link Controller-Digital (BDLC-D)
MOTOROLA
4.5.5.2 Receiving a Message in Block Mode
Although not a part of the SAE J1850 protocol, the BDLC does allow for a special
block mode of operation of the receiver. As far as the BDLC is concerned, a block
mode message is simply a long J1850 frame that contains an indefinite number of
data bytes. All of the other features of the frame remain the same, including the
SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first inform all other
nodes on the network that this is about to happen. This is usually accomplished by
sending a special predefined message.
4.5.5.3 Transmitting a Message in Block Mode
A block mode message is transmitted inherently by simply loading the bytes one
by one into the BDR register until the message is complete. The programmer
should wait until the TDRE flag (see 4.6.4 BDLC State Vector Register) is set
prior to writing a new byte of data into the BDR register. The BDLC does not contain
any predefined maximum J1850 message length requirement.
4.5.5.4 J1850 Bus Errors
The BDLC detects several types of transmit and receive errors which can occur
during the transmission of a message onto the J1850 bus.
Transmission Error
If the message transmitted by the BDLC contains invalid bits or framing symbols
on non-byte boundaries, this constitutes a transmission error. When a
transmission error is detected, the BDLC immediately will cease transmitting.
The error condition ($1C) is reflected in the BSVR register (see Table 4-5). If
the interrupt enable bit (IE in BCR1) is set, a CPU interrupt request from the
BDLC is generated.
CRC Error
A cyclical redundancy check (CRC) error is detected when the data bytes and
CRC byte of a received message are processed and the CRC calculation result
is not equal to $C4. The CRC code will detect any single and 2-bit errors, as well
as all 8-bit burst errors and almost all other types of errors. The CRC error flag
($18 in BSVR) is set when a CRC error is detected. (See 4.6.4 BDLC State
Vector Register.)
Symbol Error
A symbol error is detected when an abnormal (invalid) symbol is detected in a
message being received from the J1850 bus. However, if the BDLC is
transmitting when this happens, it will be treated as a loss of arbitration ($14 in
BSVR) rather than a transmitter error. The ($1C) symbol invalid or the
out-of-range flag is set when a symbol error is detected. Therefore, ($1C)
symbol invalid flag is stacked behind the ($14) LOA flag during a transmission
error process. (See 4.6.4 BDLC State Vector Register.)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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