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MC68HC08AS32A Datasheet(PDF) 83 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 83 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
BDLC Protocol Handler
MC68HC08AS32A — Rev. 1
Data Sheet
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
83
Framing Error
A framing error is detected if an EOD or EOF symbol is detected on a non-byte
boundary from the J1850 bus. A framing error also is detected if the BDLC is
transmitting the EOD and instead receives an active symbol. The ($1C) symbol
invalid or the out-of-range flag is set when a framing error is detected. (See
4.6.4 BDLC State Vector Register.)
Bus Fault
If a bus fault occurs, the response of the BDLC will depend upon the type of bus
fault.
If the bus is shorted to battery, the BDLC will wait for the bus to fall to a passive
state before it will attempt to transmit a message. As long as the short remains,
the BDLC will never attempt to transmit a message onto the J1850 bus.
If the bus is shorted to ground, the BDLC will see an idle bus, begin to transmit
the message, and then detect a transmission error ($1C in BSVR), since the
short to ground would not allow the bus to be driven to the active (dominant)
SOF state. The BDLC will abort that transmission and wait for the next CPU
command to transmit.
In any case, if the bus fault is temporary, as soon as the fault is cleared, the
BDLC will resume normal operation. If the bus fault is permanent, it may result
in permanent loss of communication on the J1850 bus. (See 4.6.4 BDLC State
Vector Register.)
BREAK — Break
If a BREAK symbol is received while the BDLC is transmitting or receiving, an
invalid symbol ($1C in BSVR) interrupt will be generated. Reading the BSVR
register (see 4.6.4 BDLC State Vector Register) will clear this interrupt
condition. The BDLC will wait for the bus to idle, then wait for a start-of-frame
(SOF) symbol.
The BDLC cannot transmit a BREAK symbol. It can only receive a BREAK
symbol from the J1850 bus.
4.5.5.5 Summary
Table 4-1. BDLC J1850 Bus Error Summary
Error Condition
BDLC Function
Transmission error
For invalid bits or framing symbols on non-byte boundaries, invalid symbol
interrupt will be generated. BDLC stops transmission.
Cyclical redundancy check (CRC) error
CRC error interrupt will be generated. The BDLC will wait for SOF.
Invalid symbol: BDLC receives invalid bits
(noise)
The BDLC will abort transmission immediately. Invalid symbol interrupt will be
generated.
Framing error
Invalid symbol interrupt will be generated. The BDLC will wait for SOF.
Bus short to VDD
The BDLC will not transmit until the bus is idle.
Bus short to GND
Thermal overload will shut down physical interface. Fault condition is reflected in
BSVR as an invalid symbol.
BDLC receives BREAK symbol
The BDLC will wait for the next valid SOF. Invalid symbol interrupt will be
generated.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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