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MC68HC08AS32A Datasheet(PDF) 84 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 84 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
Data Sheet
MC68HC08AS32A — Rev. 1
84
Byte Data Link Controller-Digital (BDLC-D)
MOTOROLA
4.6 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the BDLC and
consists of five user registers.
BDLC analog and roundtrip delay register (BARD)
BDLC control register 1 (BCR1)
BDLC control register 2 (BCR2)
BDLC state vector register (BSVR)
BDLC data register (BDR)
Figure 4-16. BDLC Block Diagram
4.6.1 BDLC Analog and Roundtrip Delay Register
This register programs the BDLC to compensate for various delays of different
external transceivers. The default delay value is16
µs. Timing adjustments from
9
µs to 24 µs in steps of 1 µs are available. The BARD register can be written only
once after each reset, after which they become read-only bits. The register may be
read at any time.
CPU INTERFACE
TO J1850 BUS
MUX INTERFACE
PROTOCOL HANDLER
PHYSICAL INTERFACE
TO CPU
BDLC
Address:
$003B
Bit 7
654321
Bit 0
Read:
ATE
RXPOL
00
BO3
BO2
BO1
BO0
Write:
R
R
Reset:
11000111
R= Reserved
Figure 4-17. BDLC Analog and Roundtrip Delay Register (BARD)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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