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MC68HC08AS32A Datasheet(PDF) 86 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 86 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
Data Sheet
MC68HC08AS32A — Rev. 1
86
Byte Data Link Controller-Digital (BDLC-D)
MOTOROLA
4.6.2 BDLC Control Register 1
This register is used to configure and control the BDLC.
IMSG — Ignore Message Bit
This bit is used to disable the receiver until a new start-of-frame (SOF) is
detected.
1 = Disable receiver. When set, all BDLC interrupt requests will be masked
and the status bits will be held in their reset state. If this bit is set while
the BDLC is receiving a message, the rest of the incoming message will
be ignored.
0 = Enable receiver. This bit is cleared automatically by the reception of an
SOF symbol or a BREAK symbol. It will then generate interrupt requests
and will allow changes of the status register to occur. However, these
interrupts may still be masked by the interrupt enable (IE) bit.
CLKS — Clock Bit
The nominal BDLC operating frequency (fBDLC) must always be 1.048576 MHz
or 1 MHz for J1850 bus communications to take place. The CLKS register bit
allows the user to select the frequency (1.048576 MHz or 1 MHz) used to adjust
symbol timing automatically.
1 = Binary frequency (1.048576 MHz) selected for fBDLC
0 = Integer frequency (1 MHz) selected for fBDLC
R1 and R0 — Rate Select Bits
These bits determine the amount by which the frequency of the MCU
CGMXCLK signal is divided to form the MUX interface clock (fBDLC) which
defines the basic timing resolution of the MUX interface. They may be written
only once after reset, after which they become read-only bits.
The nominal frequency of fBDLC must always be 1.048576 MHz or 1.0 MHz for
J1850 bus communications to take place. Hence, the value programmed
into these bits is dependent on the chosen MCU system clock frequency per
Table 4-3.
Address:
$003C
Bit 7
654321
Bit 0
Read:
IMSG
CLKS
R1
R0
00
IE
WCM
Write:
R
R
Reset:
11100000
R= Reserved
Figure 4-18. BDLC Control Register 1 (BCR1)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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