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MC68HC08AS32A Datasheet(PDF) 88 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 88 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
Data Sheet
MC68HC08AS32A — Rev. 1
88
Byte Data Link Controller-Digital (BDLC-D)
MOTOROLA
4.6.3 BDLC Control Register 2
This register controls transmitter operations of the BDLC. It is recommended that
BSET and BCLR instructions be used to manipulate data in this register to ensure
that the register’s content does not change inadvertently.
ALOOP — Analog Loopback Mode Bit
This bit determines whether the J1850 bus will be driven by the analog physical
interface’s final drive stage. The programmer can use this bit to reset the BDLC
state machine to a known state after the off-chip analog transceiver is placed in
loopback mode. When the user clears ALOOP, to indicate that the off-chip
analog transceiver is no longer in loopback mode, the BDLC waits for an EOF
symbol before attempting to transmit.
1 = Input to the analog physical interface’s final drive stage is looped back to
the BDLC receiver. The J1850 bus is not driven.
0 = The J1850 bus will be driven by the BDLC. After the bit is cleared, the
BDLC requires the bus to be idle for a minimum of end-of-frame symbol
time (tTRV4) before message reception or a minimum of inter-frame
symbol time (tTRV6) before message transmission. (See 18.15 BDLC
Receiver VPW Symbol Timings.)
DLOOP — Digital Loopback Mode Bit
This bit determines the source to which the digital receive input (BDRxD) is
connected and can be used to isolate bus fault conditions (see Figure 4-15). If
a fault condition has been detected on the bus, this control bit allows the
programmer to connect the digital transmit output to the digital receive input. In
this configuration, data sent from the transmit buffer will be reflected back into
the receive buffer. If no faults exist in the BDLC, the fault is in the physical
interface block or elsewhere on the J1850 bus.
1 = When set, BDRxD is connected to BDTxD. The BDLC is now in digital
loopback mode.
0 = When cleared, BDTxD is not connected to BDRxD. The BDLC is taken
out of digital loopback mode and can now drive the J1850 bus normally.
RX4XE — Receive 4X Enable Bit
This bit determines if the BDLC operates at normal transmit and receive speed
(10.4 kbps) or receive only at 41.6 kbps. This feature is useful for fast download
of data into a J1850 node for diagnostic or factory programming of the node.
1 = When set, the BDLC is put in 4X receive-only operation.
0 = When cleared, the BDLC transmits and receives at 10.4 kbps.
Address:
$003D
Bit 7
654321
Bit 0
Read:
ALOOP
DLOOP
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
Write:
Reset:
11000000
Figure 4-19. BDLC Control Register 2 (BCR2)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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