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MC68HC08AS32A Datasheet(PDF) 93 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 93 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
MC68HC08AS32A — Rev. 1
Data Sheet
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
93
transmission. When the last byte of the IFR has been loaded into the BDR, the
programmer should set the TEOD bit in the BCR2. This will instruct the BDLC
to transmit an EOD symbol once the byte in the BDR is transmitted, indicating
the end of the IFR portion of the message frame. The BDLC will not append a
CRC when the TMIFR0 is set.
If the programmer attempts to set the TMIFR0 bit after the EOD symbol has
been received from the bus, the TMIFR0 bit will remain in the reset state, and
no attempt will be made to transmit an IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting, the TMIFR0 bit will
be cleared and no attempt will be made to retransmit the byte in the BDR. If loss
of arbitration occurs in the last two bits of the IFR byte, two additional 1 bits
(active short bits) will be sent out.
NOTE:
The extra logic 1s are an enhancement to the J1850 protocol which forces a byte
boundary condition fault. This is helpful in preventing noise from going onto the
J1850 bus from a corrupted message.
4.6.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead associated
with servicing interrupts while under operation of a multiplex protocol. It provides
an index offset that is directly related to the BDLC’s current state, which can be
used with a user-supplied jump table to rapidly enter an interrupt service routine.
This eliminates the need for the user to maintain a duplicate state machine in
software.
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is pending.
The encoding of these bits are listed in Table 4-5.
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the BDLC
data register needs servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and
RDRF can be cleared only by a read of the BSVR followed by a read of the
BDLC data register (BDR). TDRE can either be cleared by a read of the BSVR
followed by a write to the BDLC BDR or by setting the TEOD bit in BCR2.
Address:
$003E
Bit 7
654321
Bit 0
Read:
0
0
I3I2I1I0
0
0
Write:
RRRRRRRR
Reset:
00000000
R= Reserved
Figure 4-21. BDLC State Vector Register (BSVR)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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