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MC68HC08AS32A Datasheet(PDF) 95 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 95 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
MC68HC08AS32A — Rev. 1
Data Sheet
MOTOROLA
Byte Data Link Controller-Digital (BDLC-D)
95
4.6.5 BDLC Data Register
This register is used to pass the data to be transmitted to the J1850 bus from the
CPU to the BDLC. It is also used to pass data received from the J1850 bus to the
CPU. Each data byte (after the first one) should be written only after a Tx data
register empty (TDRE) state is indicated in the BSVR.
Data read from this register will be the last data byte received from the J1850 bus.
This received data should only be read after an Rx data register full (RDRF)
interrupt has occurred. (See 4.6.4 BDLC State Vector Register.)
The BDR is double buffered via a transmit shadow register and a receive shadow
register. After the byte in the transmit shift register has been transmitted, the byte
currently stored in the transmit shadow register is loaded into the transmit shift
register. Once the transmit shift register has shifted the first bit out, the TDRE flag
is set, and the shadow register is ready to accept the next data byte. The receive
shadow register works similarly. Once a complete byte has been received, the
receive shift register stores the newly received byte into the receive shadow
register. The RDRF flag is set to indicate that a new byte of data has been received.
The programmer has one BDLC byte reception time to read the shadow register
and clear the RDRF flag before the shadow register is overwritten by the newly
received byte.
To abort an in-progress transmission, the programmer should stop loading data
into the BDR. This will cause a transmitter underrun error and the BDLC
automatically will disable the transmitter on the next non-byte boundary. This
means that the earliest a transmission can be halted is after at least one byte plus
two extra logic 1s have been transmitted. The receiver will pick this up as an error
and relay it in the state vector register as an invalid symbol error.
NOTE:
The extra logic 1s are an enhancement to the J1850 protocol which forces a byte
boundary condition fault. This is helpful in preventing noise from going onto the
J1850 bus from a corrupted message.
Address: $003F
Bit 7
654321
Bit 0
Read:
D7
D6
D5
D4
D3
D2
D1
D0
Write:
Reset:
Unaffected by reset
Figure 4-22. BDLC Data Register (BDR)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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