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MC68HC08AS32A Datasheet(PDF) 96 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 96 Page - Motorola, Inc

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Byte Data Link Controller-Digital (BDLC-D)
Data Sheet
MC68HC08AS32A — Rev. 1
96
Byte Data Link Controller-Digital (BDLC-D)
MOTOROLA
4.7 Low-Power Modes
The following information concerns wait mode and stop mode.
4.7.1 Wait Mode
This power-conserving mode is entered automatically from run mode whenever the
CPU executes a WAIT instruction and the WCM bit in BDLC control register 1
(BCR1) is previously clear. In BDLC wait mode, the BDLC cannot drive any data.
A subsequent successfully received message, including one that is in progress at
the time that this mode is entered, will cause the BDLC to wake up and generate a
CPU interrupt request if the interrupt enable (IE) bit in the BDLC control register 1
(BCR1) is previously set. (See 4.6.2 BDLC Control Register 1 for a better
understanding of IE.) This results in less of a power saving, but the BDLC is
guaranteed to receive correctly the message which woke it up, since the BDLC
internal operating clocks are kept running.
NOTE:
Ensuring that all transmissions are complete or aborted before putting the BDLC
into wait mode is important.
4.7.2 Stop Mode
This power-conserving mode is entered automatically from run mode whenever the
CPU executes a STOP instruction or if the CPU executes a WAIT instruction and
the WCM bit in the BDLC control register 1 (BCR1) is previously set. This is the
lowest power mode that the BDLC can enter.
A subsequent passive-to-active transition on the J1850 bus will cause the BDLC to
wake up and generate a non-maskable CPU interrupt request. When a STOP
instruction is used to put the BDLC in stop mode, the BDLC is not guaranteed to
correctly receive the message which woke it up, since it may take some time for
the BDLC internal operating clocks to restart and stabilize. If a WAIT instruction is
used to put the BDLC in stop mode, the BDLC is guaranteed to correctly receive
the byte which woke it up, if and only if an end-of-frame (EOF) has been detected
prior to issuing the WAIT instruction by the CPU. Otherwise, the BDLC will not
correctly receive the byte that woke it up.
If this mode is entered while the BDLC is receiving a message, the first subsequent
received edge will cause the BDLC to wake up immediately, generate a CPU
interrupt request, and wait for the BDLC internal operating clocks to restart and
stabilize before normal communications can resume. Therefore, the BDLC is not
guaranteed to receive that message correctly.
NOTE:
It is important to ensure all transmissions are complete or aborted prior to putting
the BDLC into stop mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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