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MC68HC08AS32A Datasheet(PDF) 99 Page - Motorola, Inc

No. de Pieza. MC68HC08AS32A
Descripción  Microcontrollers
Descarga  296 Pages
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Fabricante  MOTOROLA [Motorola, Inc]
Página de inicio  http://www.freescale.com
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MC68HC08AS32A Datasheet(HTML) 99 Page - Motorola, Inc

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Clock Generator Module (CGM)
Functional Description
MC68HC08AS32A — Rev. 1
Data Sheet
MOTOROLA
Clock Generator Module (CGM)
99
5.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external
crystal. The OSC1 pin is the input and the OSC2 pin is the output to the amplifier.
The SIMOSCEN signal from the system integration module (SIM) enables the
crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate
equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK,
the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for
operation. The duty cycle of CGMXCLK is not guaranteed to be 50% and depends
on external factors, including the crystal and related external components.
An externally generated clock also can feed the OSC1 pin of the crystal oscillator
circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
5.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or
tracking mode, depending on the accuracy of the output frequency. The PLL can
change between acquisition and tracking modes either automatically or manually.
While reading this section, refer to 18.9 CGM Operating Conditions for operating
frequencies.
Addr.
Register Name
Bit 7
654321
Bit 0
$001C
PLL Control Register
(PCTL)
See page 107.
Read:
PLLIE
PLLF
PLLON
BCS
1111
Write:
RRRR
Reset:
00101111
$001D
PLL Bandwidth Control Register
(PBWC)
See page 108.
Read:
AUTO
LOCK
ACQ
XLD
0000
Write:
RRRR
Reset:
00000000
$001E
PLL Programming Register
(PPG)
See page 110.
Read:
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
Write:
Reset:
01100110
= Unimplemented
R
= Reserved
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 5-2. CGM I/O Register Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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