IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
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San Jose, CA 95134
408-943-2600
Contact: info@Fillfactory.com
Document #: 38-05708 Rev.**(Revision 1.3 )
Page 34 of 63
Sync of left
shift-register
Sync of right
shift-register
Line n
Treg_int
Last line, followed by sync
of left shift-register
Tint
Sync
Figure 18: Syncing of the Y-shift registers.
Treg_int Difference between left and right pointer = integration counter until value “n”
of INT_TIME register is reached = INT_TIME register.
In case of NDR = 0, the actual integration time Tint is given by
Tint
Integration time [# lines] = NROF_LINES register - INT_TIME register + 1
In case of NDR = 1, NDR mode 1, the time Tint between two readings of the same row
is given by
Tint
Integration time [# lines] = NROF_LINES register + 1
In case of NDR = 1, NDR mode 2, the times Tint1 and Tint2 between two readings of
the same row (alternatingly) are given by
Tint1
Integration time [# lines] = 2 * INT_TIME register + 1
Tint2 Integration time [# lines]
= 2 * (NROF_LINES register + 1) – (2 * INT_TIME register + 1)
3.9.2.e
DELAY register
The DELAY register can be used to delay the PIXEL_VALID pulse (bits 0:3) and the
EOL/EOF pulses (bits 4:7) to synchronize them to the real pixel values at the analog
output or the ADC output (which give additional delays depending on their settings).
The bit settings and corresponding delay is indicated in Table 15.
Table 15: Delay added by changing the settings of the DELAY register
bits
Delay [# SYS_CLOCK periods]
bits
Delay [# SYS_CLOCK periods]
0000
0
1000
6
0001
0
1001
7
0010
0
1010
8
0011
1
1011
9
0100
2
1100
10
0101
3
1101
11