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IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: info@Fillfactory.com
Document #: 38-05708 Rev.**(Revision 1.3 )
Page 38 of 63
The elementary unit cell is shown in Figure 18. 16 of these cells connected in series,
having a common SPI_CLK form the entire uploadable parameter block, where Dout of
one cell is connected to SPI_DATA of the next cell (max. speed 20 MHz). The
uploaded settings on the address/data bus are loaded into the correct register of the
sensor on the rising edge of signal REG_CLOCK and become effective immediately.
D
Q
C
D
Q
C
SPI_DATA
To address/data bus
Dout
SPI_CLK
REG_CLOCK
16 outputs to address/data bus
SPI_CLK
SPI_DATA
Unity Cell
Entire uploadable address block
REG_CLOCK
A3
A2
A1
D0
REG_CLOCK
SPI_CLK
SPI_DATA
Internal register
upload
Figure 19: Schematic and timing of the SPI interface