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IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: info@Fillfactory.com
Document #: 38-05708 Rev.**(Revision 1.3 )
Page 39 of 63
4 Timing diagrams
4.1 Sequencer control signals
There are 3 control signals that operate the image sensor:
• SYS_CLOCK
• Y_CLOCK
• Y_START
These control signals should be generated by the external system with following time
constraints to SYS_CLOCK (rising edge = active edge):
TSETUP >7.5 ns.
THOLD > 7.5 ns.
It is important that these signals are free of any glitches.
Figure 20: Relative timing of the 3 sequencer control signals
Figure 21 shows the recommended schematic for generating the control signals and to
avoid any timing problems.
4.2 Basic frame and line timing
The basic frame and line timing of the IBIS4-6600 sensor is shown in Figure 21.
FF
SYS_CLOCK_N
SYS_CLOCK
Y_CLOCK
Y_START
Figure 21: Recommended schematic for generating control signals