41 / 63 page
IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: info@Fillfactory.com
Document #: 38-05708 Rev.**(Revision 1.3 )
Page 41 of 63
22). The PIXEL_VALID and EOL / EOF pulses can be delayed by the user through the
DELAY register.
T1
Row blanking time (see Table 14)
T2
4 SYS_CLOCK cycles.
Figure 23: Pixel output timing (two outputs).
4.3.2 Multiplexing to one output
The pixel signal at the OUT1 output becomes valid after 5 SYS_CLOCK cycles when
the internal X_SYNC (= start of PIXEL_VALID output) has appeared (see Figure 23).
The PIXEL_VALID and EOL / EOF pulses can be delayed by the user through the DELAY
register.
T1
Row blanking time
T2
5 SYS_CLOCK cycles.
Figure 24: Pixel output timing (one output)
N-1