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IBIS4-6600 Datasheet(PDF) 43 Page - Cypress Semiconductor

No. de pieza IBIS4-6600
Descripción Electrónicos  High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor
Download  63 Pages
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Fabricante Electrónico  CYPRESS [Cypress Semiconductor]
Página de inicio  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

IBIS4-6600 Datasheet(HTML) 43 Page - Cypress Semiconductor

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IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: info@Fillfactory.com
Document #: 38-05708 Rev.**(Revision 1.3 )
Page 43 of 63
5 Pin list
Table 17 is a list of all the pins and their function. In total, there are 68 pins. All pins
with the same name can be connected together.
Table 17: Pin list
Pin Pin name
Pin
type
Expected
Voltage [V]
Pin description
1
CMD_COL_CTU
Input
0
Biasing of columns (ctu). Decouple
with 100 nF to GNDA.
2
CMD_COL
Input
1.08
Biasing of columns. Connect to VDDA
with R = 10 k
Ω and decouple to GNDA
with C = 100 nF.
3
CMD_COLAMP
Input
0.66
Biasing of column amplifiers. Connect
to VDDA with R = 100 k
Ω and
decouple to GNDA with C = 100 nF.
4
CMD_COLAMP_CTU
Input
0.37
Biasing of column amplifiers. Connect
to VDDA with R = 10 M
Ω and
decouple to GNDA with C = 100 nF.
5
RCAL_DAC_DARK
Input
1.27 @ code
128
DAC_DARK
reg
Biasing of DAC for dark reference.
Can be used to set output range of
DAC.
Default: decouple to GNDA with C =
100 nF.
6
RCAL_DAC_OUT
Input
0
Biasing of DAC for output dark level.
Can be used to set output range of
DAC. Default: connect to GNDA.
7
VDDA
Power
2.5
VDD of analog part [2.5 V].
8
GNDA
Power
0
GND (&substrate) of analog part.
9
VDDD
Power
2.5
VDD of digital part [2.5 V].
10
GNDD
Power
0
GND (&substrate) of digital part.
11
CMD_OUT_1
Input
0.78
Biasing of first stage output amplifiers.
Connect to VDDAMP with R = 50 k
and decouple to GNDAMP with C =
100 nF.
12
CMD_OUT_2
Input
0.97
Biasing of second stage output
amplifiers. Connect to VDDAMP with
R = 25 k
Ω and decouple to GNDAMP
with C = 100 nF.
13
CMD_OUT_3
Input
0.67
Biasing of third stage output amplifiers.
Connect to VDDAMP with R = 100 k
and decouple to GNDAMP with C =
100 nF.
14
SPI_CLK
Input
-
Clock of digital parameter upload.
Shifts on rising edge.
15
SPI_DATA
Input
-
Serial address and data input. 16 bit
word. Address first. MSB first.
16
VDDAMP
Power
2.5
VDD of analog output [2.5 V] (Can be
connected to VDDA).


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