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IBIS4-6600 Datasheet(PDF) 44 Page - Cypress Semiconductor

No. de Pieza. IBIS4-6600
Descripción  High resolution 6.6 M Pixel Rolling shutter CMOS Image sensor
Descarga  63 Pages
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Fabricante  CYPRESS [Cypress Semiconductor]
Página de inicio  http://www.cypress.com
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IBIS4-6600 Datasheet(HTML) 44 Page - Cypress Semiconductor

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IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: info@Fillfactory.com
Document #: 38-05708 Rev.**(Revision 1.3 )
Page 44 of 63
Pin Pin name
Pin
type
Expected
Voltage [V]
Pin description
17
CMD_FS_ADC
Input
0.73
Biasing of first stage ADC. Connect to
VDDA_ADC with R = 50 k
Ω and
decouple to GNDA_ADC with C = 100
nF.
18
CMD_SS_ADC
Input
0.73
Biasing of second stage ADC. Connect
to VDDA_ADC with R = 50 k
Ω and
decouple to GNDA_ADC.
19
CMD_AMP_ADC
input
0.59
Biasing of input stage ADC. Connect to
VDDA_ADC with R = 180 k
Ω and
decouple to GNDA_ADC with C = 100
nF.
20
GNDAMP
Ground 0
GND (&substrate) of analog output.
21
OUT1
Output
Black level: 1
@ code 190
DAC_RAW reg.
Analog output 1.
22
ADC_IN1
Input
See OUT1.
Analog input ADC 1.
23
VDDAMP
Power
2.5
VDD of analog output [2.5 V] (Can be
connected to VDDA).
24
OUT2
Output
Black level: 1
@ code 190
DAC_RAW reg.
Analog output 2.
25
ADC_IN2
Input
See OUT2.
Analog input ADC 2.
26
VDDD
Power
2.5
VDD of digital part [2.5 V].
27
GNDD
Power
0
GND (&substrate) of digital part.
28
GNDA
Power
0
GND (&substrate) of analog part.
29
VDDA
Power
2.5
VDD of analog part [2.5 V].
30
REG_CLOCK
Input
-
Register clock. Data on internal bus is
copied to corresponding registers on
rising edge.
31
SYS_CLOCK
Input
-
System clock defining the pixel rate.
32
SYS_RESET
Input
-
Global system reset.
33
Y_CLK
Input
-
Line clock.
34
Y_START
Input
-
Start frame readout.
35
GNDD_ADC
Power
0
GND (&substrate) of digital part ADC.
36
VDDD_ADC
Power
2.5
VDD of digital part [2.5 V] ADC.
37
GNDA_ADC
Power
0
GND (&substrate) of analog part.
38
VDDA_ADC
Power
2.5
VDD of analog part [2.5 V].
39
VHIGH_ADC
Input
2.37
ADC high reference voltage (e.g.
connect to VDDA_ADC with R = 144
Ω and decouple to GNDA_ADC with C
= 100 nF.
40
VLOW_ADC
Input
0.59
ADC low reference voltage (e.g.
connect to GNDA_ADC with R = 59 Ω
and decouple to GNDA_ADC with C =
100 nF.
41
GNDA_ADC
Power
0
GND (&substrate) of analog part.
42
VDDA_ADC
Power
2.5
VDD of analog part [2.5 V].
43
GNDD_ADC
Power
0
GND (&substrate) of digital part ADC.
44
VDDD_ADC
Power
2.5
VDD of digital part [2.5 V] ADC.


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