IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: info@Fillfactory.com
Document #: 38-05708 Rev.**(Revision 1.3 )
Page 45 of 63
Pin Pin name
Pin
type
Expected
Voltage [V]
Pin description
45
VDD_RESET_DS
Power
2.5 (for no
dual slope)
Variable reset voltage (dual slope).
46
ADC_CLK_EXT
Input
-
External ADC clock.
47
EOL
Output
-
Diagnostic end of line signal (produced
by sequencer), can be used as Y_CLK.
48
EOF
Output
-
Diagnostic end of frame signal
(produced by sequencer), can be used
as Y_START.
49
PIX_VALID
Output
-
Diagnostic signal. High during pixel
readout.
50
TEMP
Output
-
Temperature measurement. Output
voltage varies linearly with
temperature.
51
ADC_D<9>
Output
-
ADC data output (MSB).
52
VDD_PIX
Power
2.5
VDD of pixel core [2.5 V].
53
GND_AB
Power
0
Anti-blooming ground. Set to 1 V for
improved anti-blooming behavior.
54
ADC_D<8>
Output
-
ADC data output.
55
ADC_D<7>
Output
-
ADC data output.
56
ADC_D<6>
Output
-
ADC data output.
57
ADC_D<5>
Output
-
ADC data output.
58
ADC_D<4>
Output
-
ADC data output.
59
ADC_D<3>
Output
-
ADC data output.
60
VDD_RESET
Power
2.5
Reset voltage [2.5 V]. Highest voltage
to the chip. 3.3 V for extended dynamic
range or ‘hard reset’.
61
ADC_D<2>
Output
-
ADC data output.
62
ADC_D<1>
Output
-
ADC data output.
63
ADC_D<0>
Output
-
ADC data output (LSB).
64
BS_RESET
Input
-
Boundary scan (allows debugging of
internal nodes): reset.
65
BS_CLOCK
Input
-
Boundary scan (allows debugging of
internal nodes): clock.
66
BS_DIN
Input
-
Boundary scan (allows debugging of
internal nodes): in.
67
BS_BUS
Output
-
Boundary scan (allows debugging of
internal nodes): bus.
68
CMD_DEC
Input
0.74
Biasing of X and Y decoder. Connect
to VDDD with R = 50 kΩ and decouple
to GNDD with C = 100 nF.
Note on power-on behavior
At power-on, the chip is in an undefined state. It is advised that the power-on is
accompanied by the assertion of the SYS_CLOCK and a SYS_RESET pulse that puts all
internal registers in their default state (all bits are set to 0). The X-shift registers are in
a defined state after the first X_SYNC which occurs a few microseconds after the first
Y_START and Y_CLOCK pulse. Prior to this X_SYNC, the chip may draw more current
from the analog power supply VDDA. It is therefore favorable to have separate analog