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IBIS4-6600
Datasheet
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: info@Fillfactory.com
Document #: 38-05708 Rev.**(Revision 1.3 )
Page 16 of 63
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bus1_S
bus1_R
bus2_S
bus2_R
DAC_raw /
DAC_fine
analog
multiplexer
programmable
gain amplifiers
Pixel output 1
Pixel output 2
A2
A1
S2
S1
1
1
output
drivers
DAC_dark
Stage 1
Stage 2
Stage 3
Figure 8: Output amplifier architecture
3.5.1 Stage 1: Offset, FPN correction and multiplexing
In the first stage, the signals from the busses are subtracted and the offset from the
DACs is added. After a system reset, the analog multiplexer is configured for two
outputs (see bit settings of the AMPLIFIER register). In case ONE_OUT is set to 1, the
two signals S1 and S2 are multiplexed to one output (output 1). The amplifiers of
stage 2 and stage 3 of the second output path are then put in standby. The speed and
power consumption of the first stage is controllable through the resistor connected to
CMD_OUT_1.
3.5.2 Stage 2: Programmable gain amplifier
The second stage provides the gain which will be adjustable between 1.36 and 17.38
in steps of roughly 20.25 (~1.2). An overview of the gain settings is given in Table 8
and Figure 9. The speed and power consumption of the second stage is controllable
through the resistor connected to CMD_OUT_2.