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SN74SSTU32864C Datasheet(PDF) 11 Page - Texas Instruments

No. de Pieza. SN74SSTU32864C
Descripción  25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL 18 INPUTS AND OUTPUTS
Descarga  18 Pages
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Fabricante  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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SN74SSTU32864C Datasheet(HTML) 11 Page - Texas Instruments

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Electrical Characteristics
Timing Requirements
(1)
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES542A – JANUARY 2004 – REVISED FEBRUARY 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(1)
MAX
UNIT
IOH = –100 µA
1.7 V to 1.9 V
VCC – 0.2
VOH
V
IOH = –6 mA
1.7 V
1.3
IOL = 100 µA
1.7 V to 1.9 V
0.2
VOL
V
IOL = 6 mA
1.7 V
0.4
II
All inputs(2)
VI = VCC or GND
1.9 V
±5
µA
Static standby
RESET = GND
100
µA
ICC
IO = 0
1.9 V
Static operating
RESET = VCC, VI = VIH(AC) or VIL(AC)
40
mA
Dynamic operating –
RESET = VCC, VI = VIH(AC) or VIL(AC),
33
µA/MHz
clock only
CLK and CLK switching 50% duty cycle
Dynamic operating –
per each data input,
19
RESET = VCC, VI = VIH(AC) or VIL(AC),
µA/
ICCD
IO = 0
1.8 V
1:1 configuration
CLK and CLK switching 50% duty cycle,
clock
One data input switching at one-half
MHz/
Dynamic operating –
clock frequency, 50% duty cycle
D input
per each data input,
35
1:2 configuration
Chip-select-enabled
RESET = VCC, VI = VIH(AC) or VIL(AC),
low-power active
34
µA/MHz
CLK and CLK switching 50% duty cycle
mode, clock only
Chip-select-enabled
low-power active
2
ICCDLP
mode, 1:1
IO = 0
1.8 V
RESET = VCC, VI = VIH(AC) or VIL(AC),
µA/
configuration
CLK and CLK switching 50% duty cycle,
clock
One data input switching at one-half
MHz/
Chip-select-enabled
clock frequency, 50% duty cycle
D input
low-power active
2
mode, 1:2
configuration
Data inputs, CSR
VI = VREF ± 250 mV
2.5
3
3.5
Ci
CLK, CLK
VICR = 0.9 V, VI(PP) = 600 mV
1.8 V
2
3
pF
RESET
VI = VCC or GND
2.5
(1)
All typical values are at VCC = 1.8 V, TA = 25°C.
(2)
Each VREF pin (A3 or T3) should be tested independently, with the other (untested) pin open.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
MIN
MAX
UNIT
fclock
Clock frequency
500
MHz
tw
Pulse duration, CLK, CLK high or low
1
ns
tact
Differential inputs active time(2)
10
ns
tinact
Differential inputs inactive time(3)
15
ns
DCS before CLK
↑, CLK↓, CSR high; CSR before CLK↑, CLK↓, DCS high
0.6
tsu
Setup time
DCS before CLK
↑, CLK↓, CSR low
0.5
ns
DODT, DCKE, and Data before CLK
↑, CLK↓
0.5
th
Hold time
DCS, DODT, DCKE, and Data after CLK
↑, CLK↓
0.5
ns
(1)
All input slew rates are 1 V/ns
±20%.
(2)
VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max after RESET is taken high.
(3)
VREF data and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max after RESET is taken low.
11


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