Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼

Delete All
ON OFF
ALLDATASHEET.ES

X  

Preview PDF Download HTML

SN74SSTU32864C Datasheet(PDF) 13 Page - Texas Instruments

No. de Pieza. SN74SSTU32864C
Descripción  25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL 18 INPUTS AND OUTPUTS
Descarga  18 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  TI [Texas Instruments]
Página de inicio  http://www.ti.com
Logo 

SN74SSTU32864C Datasheet(HTML) 13 Page - Texas Instruments

Zoom Inzoom in Zoom Outzoom out
 13 / 18 page
background image
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC/2
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 Ω,
input slew rate = 1 V/ns
±20% (unless otherwise noted).
D. The outputs are measured one at a time, with one transition per measurement.
E. VREF = VCC/2
F. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
G. VIL = VREF − 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
H. VI(PP) = 600 mV
I. tPLH and tPHL are the same as tpd.
0 V
VCC
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Inputs
VICR
VREF
Input
VIL
VIH
VREF
VI(PP)
tPHL
VOH
VOL
Output
VCC/2
VCC/2
tPLH
tPHL
VIH
VIL
VOL
VOH
LVCMOS
RESET
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
VCC/2
VI(PP)
VICR
Timing
Inputs
VICR
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
VREF
Input
VREF
tw
VOLTAGE WAVEFORMS
PULSE DURATION
VIH
VIL
LVCMOS
RESET
Input
tact
tinact
10%
90%
ICC (operating)
ICC (standby)
ICC
(see
Note B)
Clock Inputs
LOAD CIRCUIT
RL = 1 kΩ
VCC
ZO = 50 Ω,
tD = 350 ps
ZO = 50 Ω,
tD = 350 ps
CL = 30 pF
(see Note A)
Output
Test Point
DUT
RL = 100 Ω
CLK
Out
CLK
ZO = 50 Ω,
tD = 350 ps
Test
Point
Test
Point
RL = 1 kΩ
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES542A – JANUARY 2004 – REVISED FEBRUARY 2005
Figure 1. Load Circuit and Voltage Waveforms
13


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18 


Datasheet Download




Enlace URL




Privacy Policy
ALLDATASHEET.ES
Does ALLDATASHEET help your business so far?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn