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ZL50062 Datasheet(PDF) 36 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 36 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
36
Zarlink Semiconductor Inc.
12.0
Internal Register Mappings
When the most significant bit, A14, of the address bus is set to ’0’, the microprocessor is performing an access to
one of the device’s internal registers. Address bits A13-A0 indicate which particular register is being accessed.
13
BE
Backplane Output Enable Bit
When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the BORS pin.
When HIGH, the channel is active.
12:8
BSAB[4:0]
Source Stream Address Bits
The binary value of these 5 bits represents the input stream number.
Ignored when BMM is set HIGH.
7:0
BCAB[7:0]
Source Channel Address Bits / Message Mode Data
The binary value of these 8 bits represents the input channel number when BMM is set
LOW.
Transmitted as data when BMM is set HIGH.
Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits
are output sequentially to the timeslot with BCAB[7] being output first.
A14-A0
Register
0000H
Control Register, CR
0001H
Block Programming Register, BPR
0023H - 0042H
Local Input Bit Delay Register 0 - 31, LIDR0 - 31
0063H - 0082H
Backplane Input Bit Delay Register 0 - 31, BIDR0 - 31
0083H - 00A2H
Local Output Advancement Register 0 - 31, LOAR0 - 31
00A3H - 00C2H
Backplane Output Advancement Register 0 - 31, BOAR0 - 31
014DH
Memory BIST Register, MBISTR
1001H
Bit Rate Register, BRR
3FFFH
Device Identification Register, DIR
Table 12 - Address Map for Registers (A14 = 0)
Bit
Name
Description
Table 11 - BCM Bits for Source-to-Backplane Switching (continued)


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