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ZL50062 Datasheet(PDF) 37 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 37 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
37
Zarlink Semiconductor Inc.
13.0
Detailed Register Descriptions
This section describes the registers that are used in the device.
13.1
Control Register (CR)
Address 0000H.
The Control Register defines which memory is to be accessed. It initiates the memory block programming mode
and selects the Backplane and Local data rate modes. The Control Register (CR) is configured as follows:
Bit
Name
Reset
Value
Description
15:13
FBD_
MODE[2:0]
0
Frame Boundary Discriminator Mode
When set to 111B, the Frame Boundary Discriminator can handle both low
frequency and high frequency jitter.
When set to 000B, the Frame Boundary Discriminator is set to handle lower
frequency jitter only.
All other values are reserved.
These bits are ignored when FBDEN bit is LOW.
12
SMPL_
MODE
0
Sample Point Mode
When LOW the input bit sampling point is always at the 3/4 bit location. The input bit
fractional delay is programmed in 1/4 bit increments from 0 to 7 3/4 as per the value
of the LIDR0 to LIDR31 and BIDR0 to BIDR31 registers.
When HIGH, the input bit sampling point is programmed to the 3/4, 4/4, 1/4, 2/4 bit
location as per the value of the LIDR0 to LIDR31 and BIDR0 to BIDR31 registers. In
addition, the incoming data can be delayed by 0 to 7 bits in 1 bit increments.
See Table 15, Table 16, Table 17 and Table 18 for details.
11
Reserved
0
Reserved
Must be set to 0 for normal operation
10
FBDEN
0
Frame Boundary Discriminator Enable
When LOW, the frame boundary discriminator function is disabled.
When HIGH, enables frame boundary discriminator function which allows the
device to tolerate inconsistent frame boundaries, hence improving the tolerance to
cycle-to-cycle variation on the input clock.
9
Reserved
0
Reserved
Must be set to 0 for normal operation
8FPW
0
Frame Pulse Width
When LOW, the user must apply a 122ns frame pulse on FP8i; the FP8o pin will
output a 122ns wide frame pulse; FP16o will output a 61ns wide frame pulse.
When HIGH, the user must apply a 244ns frame pulse on FP8i; the FP8o pin will
output a 244ns wide frame pulse; FP16o will output a 122ns wide frame pulse.
7
Reserved
0
Reserved
Must be set to 0 for normal operation
6C8IPOL
0
8MHz Input Clock Polarity
The frame boundary is aligned to the falling or rising edge of the input clock.
When LOW, the frame boundary is aligned to the clock falling edge.
When HIGH, the frame boundary is aligned to the clock rising edge.
5
COPOL
0
Output Clock Polarity
When LOW, the output clock has the same polarity as the input clock.
When HIGH, the output clock is inverted.
This applies to both the 8MHz (C8o) and 16MHz (C16o) output clocks.
Table 13 - Control Register Bits


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