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ZL50062 Datasheet(PDF) 42 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 42 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
42
Zarlink Semiconductor Inc.
13.3
Local Input Bit Delay Registers (LIDR0 to LIDR31)
Addresses 0023H to 0042H.
There are thirty-two Local Input Delay Registers (LIDR0 to LIDR31).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and LIDR0 to LIDR31 define the input bit and fractional bit delay of each Local stream. The possible bit
delay adjustment is up to 73/4 bits, in steps of
1/
4 bit.
When the SMPL_MODE bit is HIGH, LIDR0 to LIDR31 define the input bit sampling point as well as the integer bit
delay of each Local stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be
adjusted in 1-bit increments from 0 to 7 bits.
The LIDR0 to LIDR31 registers are configured as follows:
Table 15 - Local Input Bit Delay Register (LIDRn) Bits
LIDRn Bit
(where n = 0 to 31)
Name
Reset
Value
Description
15:5
Reserved
0
Reserved
Must be set to 0 for normal operation
4:0
LID[4:0]
0
Local Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit and fractional bit delay value (0
to 73/4).
When SMPL_MODE = HIGH, the binary value of LID[1:0]
refers to the input bit sampling point (1/4 to
4/
4). LID[4:2]
refer to the integer bit delay value (0 to 7 bits).


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