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ZL50062 Datasheet(PDF) 43 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 43 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
43
Zarlink Semiconductor Inc.
13.3.1
Local Input Delay Bits 4-0 (LID[4:0])
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 73/4 bit periods forward, with resolution of
1/
4 bit
period. The default sampling point is at the 3/4 bit location.
This can be described as: no. of bits delay = LID[4:0] / 4
For example, if LID[4:0] is set to 10011 (19), the input bit delay = 19 * 1/4 = 4
3/
4.
When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (1/4 to
4/
4). LID[4:2]
refer to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from 1/4 to
4/
4 in
1/
4-bit increments.
Table 16 illustrates the bit delay and sampling point selection.
LIDn
SMPL_MODE
= LOW
SMPL_MODE
= HIGH
LID4
LID3
LID2
LID1
LID0
Input Data
Bit Delay
Input Data
Bit Delay
Input Data
Sampling
Point
00000
0 (Default)
0 (Default)
3/4
00001
1/4
0
4/4
00010
1/2
0
1/4
00011
3/4
0
2/4
00100
1
1
3/4
00101
1 1/4
1
4/4
00110
1 1/2
1
1/4
00111
1 3/4
1
2/4
01000
2
2
3/4
01001
2 1/4
2
4/4
01010
2 1/2
2
1/4
01011
2 3/4
2
2/4
01100
3
3
3/4
01101
3 1/4
3
4/4
01110
3 1/2
3
1/4
01111
3 3/4
3
2/4
10000
4
4
3/4
10001
4 1/4
4
4/4
10010
4 1/2
4
1/4
10011
4 3/4
4
2/4
10100
5
5
3/4
10101
5 1/4
5
4/4
10110
5 1/2
5
1/4
10111
5 3/4
5
2/4
11000
6
6
3/4
11001
6 1/4
6
4/4
11010
6 1/2
6
1/4
11011
6 3/4
6
2/4
Table 16 - Local Input Bit Delay and Sampling Point Programming Table


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