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ZL50062 Datasheet(PDF) 46 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 46 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
46
Zarlink Semiconductor Inc.
13.5
Local Output Advancement Registers (LOAR0 to LOAR31)
Addresses 0083H to 00A2H.
Thirty-two Local Output Advancement Registers (LOAR0 to LOAR31) allow users to program the output
advancement for output data streams LSTo0 to LSTo31. The possible adjustment is -2 (15ns), -4 (31ns) or -6 (46ns)
cycles of the internal system clock (131.072MHz).
The LOAR0 to LOAR31 registers are configured as follows:
Table 19 - Local Output Advancement Register (LOAR) Bits
13.5.1
Local Output Advancement Bits 1-0 (LOA1-LOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
11011
6 3/4
6
2/4
11100
7
7
3/4
11101
7 1/4
7
4/4
11110
7 1/2
7
1/4
11111
7 3/4
7
2/4
LOARn Bit
(where n = 0 to 31)
Name
Reset
Value
Description
15:2
Reserved
0
Reserved
Must be set to 0 for normal operation
1:0
LOA[1:0]
0
Local Output Advancement Value
Local Output Advancement
Corresponding
Advancement Bits
Clock Rate 131.072 MHz
LOA1
LOA0
0 (Default)
0
0
-2 cycles (~15ns)
0
1
-4 cycles (~31ns)
1
0
-6 cycles (~46ns)
1
1
Table 20 - Local Output Advancement (LOAR) Programming Table
BIDn
SMPL_MODE
= LOW
SMPL_MODE
= HIGH
BID4
BID3
BID2
BID1
BID0
Input Data
Bit Delay
Input Data
Bit Delay
Input Data
Sampling
Point
Table 18 - Backplane Input Bit Delay and Sampling Point Programming Table (continued)


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