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ZL50062 Datasheet(PDF) 47 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 47 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
47
Zarlink Semiconductor Inc.
13.6
Backplane Output Advancement Registers (BOAR0 - BOAR31)
Addresses 00A3H to 00C2H
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR31) allow users to program the output
advancement for output data streams BSTo0 to BSTo31. The possible adjustment is -2 (15ns), -4 (31ns) or -6
(46ns) cycles of the internal system clock (131.072MHz).
The BOAR0 to BOAR31 registers are configured as follows:
Table 21 - Backplane Output Advancement Register (BOAR) Bits
13.6.1
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
13.7
Memory BIST Register
Address 014DH.
The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to
start MBIST: the first with only Bit 12 (LV_TM) set HIGH (i.e. 1000h); the second with Bit 12 maintained HIGH but
with the required start bit(s) also set HIGH.
The MBISTR register is configured as follows:
BOARn Bit
(where n = 0 to 31)
Name
Reset
Value
Description
15:2
Reserved
0
Reserved
Must be set to 0 for normal operation
1:0
BOA[1:0]
0
Backplane Output Advancement Value
Backplane Output Advancement
Corresponding
Advancement Bits
Clock Rate 131.072 MHz
BOA1
BOA0
0 (Default)
0
0
-2 cycles (~15ns)
0
1
-4 cycles (~31ns)
1
0
-6 cycles (~46ns)
1
1
Table 22 - Backplane Output Advancement (BOAR) Programming Table
Bit
Name
Reset
Value
Description
15:13
Reserved
0
Reserved
Must be set to 0 for normal operation
Table 23 - Memory BIST Register (MBISTR) Bits


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