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ZL50062 Datasheet(PDF) 49 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 49 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
49
Zarlink Semiconductor Inc.
13.8
Bit Rate Register
Address 1001H
This register allows the bit rate of all the input and output streams to be set to 2.048, 4.096, 8.192 or 16.384 Mbps.
The BRR register is configured as follows:
13.9
Device Identification Register
Address 3FFFH.
The Device Identification Register stores the binary value of the silicon revision number and the Device ID. This
register is read-only. The DIR register is configured as follows:
Table 25 - Device Identification Register (DIR) Bits
Bit
Name
Reset
Value
Description
15:3
Reserved
0
Reserved
Must be set to 0 for normal operation
2:1
BRS[1:0]
0
Bit Rate Selector
These 2 bits define the bit rate of all the input and output ST-BUS streams, which
can operate in either 2.048, 4.096, 8.192 or 16.384 Mbps.
0
Reserved
0
Reserved
Must be set to 0 for normal operation
Table 24 - Bit Rate Register (BRR) Bits
Bit
Name
Reset Value
Description
15:8
Reserved
0
Reserved
Will read 0 in normal operation
7:4
RC[3:0]
0000
Revision Control Bits
3
Reserved
0
Reserved
Will read 0 in normal operation
2:0
DID[2:0]
110
Device ID
Output Control with ODE pin and OSB bit
Bit 2
Bit 1
Bit Rate of all ST-BUS Streams
0
0
2.048Mbps
0
1
4.096Mbps
1
0
8.192Mbps
1
1
16.384Mbps


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