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ZL50062 Datasheet(PDF) 52 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 52 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
52
Zarlink Semiconductor Inc.
15.0
AC Electrical Characteristics
AC Electrical Characteristics Timing Parameter Measurement: Voltage Levels
Characteristics
Sym
Level
Units
Conditions
1
CMOS Threshold
VCT
0.5VDD_IO
V3.0V < VDD_IO < 3.6V
2
Rise/Fall Threshold Voltage High
VHM
0.7VDD_IO
V3.0V < VDD_IO < 3.6V
3
Rise/Fall Threshold Voltage Low
VLM
0.3VDD_IO
V3.0V < VDD_IO < 3.6V
Input and Output Clock Timing
Characteristic
Sym
Min
Typ
Max
Units
Notes
1FP8i, Input Frame Pulse Width
tIFPW244
tIFPW122
210
10
244
122
350
220
ns
2
Input Frame Pulse Setup Time
(before C8i clock falling/rising edge)
tIFPS244
tIfPS122
5
5
110
60
ns
3
Input Frame Pulse Hold Time
(from C8i clock falling/rising edge)
tIFPH244
tIFPH122
0
0
110
60
ns
4C8i Clock Period (Average value, does not
consider the effects of jitter)
tICP
120
122
124
ns
5C8i Clock Pulse Width High
tICH
50
61
70
ns
6C8i Clock Pulse Width Low
tICL
50
61
70
ns
7C8i Clock Rise/Fall Time
trIC, tfIC
02
3
ns
8C8i Cycle to Cycle Variation
(This values is with respect to the typical C8i
Clock Period, and using mid-bit sampling)
tCCVIC
-7.0
-8.5
7.0
8.5
ns
16Mbps
or lower.
9
Output Frame Boundary Offset
tOFBOS
79.5
ns
10
FP8o Frame Pulse Width
tOFPW8_244
tOFPW8_122
224
117
244
122
264
127
ns
FPW =1
FPW=0
CL=60pF
11
FP8o Output Delay
(from frame pulse edge to output frame
boundary)
tFPFBF8_244
tFPFBF8_122
117
58
122
61
127
64
ns
FPW =1
FPW=0
CL=60pF
12
FP8o Output Delay
(from output frame boundary to frame pulse
edge)
tFBFPF8_244
tFBFPF8_122
117
58
122
61
127
64
ns
FPW =1
FPW=0
CL=60pF
13
C8o Clock Period
tOCP8
117
122
127
ns
CL=60pF
14
C8o Clock Pulse Width High
tOCH8
58
61
64
ns
15
C8o Clock Pulse Width Low
tOCL8
58
61
64
ns
16
C8o Clock Rise/Fall Time
trOC8, tfOC8
37
ns


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