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ZL50062 Datasheet(PDF) 63 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Descarga  68 Pages
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 63 Page - Zarlink Semiconductor Inc

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ZL50062/4
Data Sheet
63
Zarlink Semiconductor Inc.
Note 1:
High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge
CL.
Note 2:
There must be a minimum of 30ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a
minimum of 30ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next
access).
Non-Multiplexed Microprocessor Port Timing
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1CS setup from DS falling
tCSS
0ns
2R/W setup from DS falling
tRWS
9ns
3
Address setup from DS falling
tADS
9ns
4CS hold after DS rising
tCSH
0ns
5R/W hold after DS rising
tRWH
9ns
6
Address hold after DS rising
tADH
9ns
7
Data setup from DTA Low on Read
tRDS
5
12
ns
ns
Memory Read
Register Read
CL=60pF
8
Data hold on read
tRDH
4.5
ns
CL=60pF, RL=1k
Note 1
9
Data setup on write
tWDS
9ns
10
Data hold on write
tWDH
9ns
11
Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
tAKD
88
80
ns
ns
CL=60pF
CL=60pF
12
Acknowledgment Hold Time
tAKH
11
ns
CL=60pF, RL=1k,
Note 1


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