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ZL50062 Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc

No. de Pieza. ZL50062
Descripción  16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
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Fabricante  ZARLINK [Zarlink Semiconductor Inc]
Página de inicio  http://www.zarlink.com
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ZL50062 Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc

 
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
Features
16,384-channel x 16,384-channel non-blocking
unidirectional switching.The Backplane and Local
inputs and outputs can be combined to form a
non-blocking switching matrix with 64 input
streams and 64 output streams
8,192-channel x 8,192-channel non-blocking
Backplane input to Local output stream switch
8,192-channel x 8,192-channel non-blocking
Local input to Backplane output stream switch
8,192-channel x 8,192-channel non-blocking
Backplane input to Backplane output switch
8,192-channel x 8,192-channel non-blocking
Local input to Local output stream switch
Backplane port accepts 32 input and 32 output
ST-BUS streams with fixed data rates of
2.048Mbps, 4.096Mbps, 8.192Mbps or
16.384Mbps
Local port accepts 32 input and 32 output ST-
BUS streams with fixed data rates of 2.048Mbps,
4.096Mbps, 8.192Mbps or 16.384Mbps
Exceptional input clock jitter tolerance (17ns)
Per-stream bit delay for Local and Backplane
input streams
Per-stream advancement for Local and Backplane
output streams
Constant 2-frame throughput delay for frame
integrity
Per-channel high impedance output control for
Local and Backplane streams
Per-channel driven-high output control for Local
and Backplane streams
Per-channel message mode for Local and
Backplane output streams
Connection memory block programming for fast
device initialization
November 2003
Ordering Information
ZL50062GAC
256-Ball PBGA
ZL50064QCC
256-Pin LQFP
-40
°C to +85°C
ZL50062/4
16K-Channel Digital Switch with High Jitter
Tolerance, Single Rate (2, 4, 8,
or 16Mbps), and 64 Inputs and 64 Outputs
Data Sheet
Figure 1 - ZL50062/4 Functional Block Diagram
Backplane Data Memories
(8,192 channels)
DS CS R/W
A14-0
DTA
D15-0
Test Port
Microprocessor Interface
and Internal Registers
VSS (GND)
VDD_CORE
TDi TDo TCK TRST
TMS
LSTo0-31
(8,192 locations)
RESET
Local
Interface
Connection Memory
BSTi0-31
Input
Timing Unit
FP8i
PLL
LSTi0-31
Interface
Backplane
BSTo0-31
Local
C8i
VDD_IO
ODE
C8o
C16o
FP8o
FP16o
VDD_PLL
Output
Timing
Unit
(8,192 locations)
Connection Memory
Backplane
Interface
Local
Local Data Memories
(8,192 channels)
BORS
LORS


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